Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic...Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.展开更多
基金supported by the National Natural Science Foundation of China(61401204)the Fundamental Research Funds for the Central Universities(30916011319)+1 种基金the Technology Research and Development Program of Jiangsu Province(BY2015004-03)the Postdoctoral Science Foundation of Jiangsu Province(1501104C)
文摘Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.
文摘在中压大功率并网逆变器中,存在开关频率低、输出滤波器设计困难等问题。采用断续脉宽调制策略(discontinuous pulse-width modulation,DPWM)能在保证开关损耗不变的前提下,有效提高逆变器等效开关频率、降低滤波器设计难度。首先,对6种三电平DPWM(DPWM0、DPWM1、DPWM2、DPWM3、DPWMA、DPWMB)的各自优缺点进行比较分析,结果表明在单位功率因数及较高调制度下,DPWMA兼具开关损耗小、共模电压与谐波畸变低的优点;其次,针对DPWMA调制策略输出谐波相对集中于第一载波带的特性,引入LLCL滤波器拓扑,并基于选频思想提出一种改进阻尼方案,在有效提高载波频率处谐波衰减能力的同时,确保谐振抑制能力且显著降低阻尼电阻损耗;随后,给出了所提滤波器的参数设计原则及其详细流程。对30 k W样机进行实验,实验结果表明,采用该文所提调制策略和滤波器设计方法,逆变器的输出共模电压和并网电流谐波含量能够得到有效降低,同时阻尼电阻损耗较小,有利于减小中压大功率逆变器的网侧滤波器体积与成本,提高系统效率。
文摘本文针对嵌入式应用中PWM(Pulse-WidthModulation)方式DAC(Digita-l to-Analog Converter)和独立DAC芯片选择问题,提出了通过插值方式和多PWM组合方式提高PWM方式DAC分辨率的方法;分析了PWM信号频谱,提出了模拟滤波器设计原则与方法.以MCU(Micro Control Unit)的PWM通道方式实现DAC,经过数据分析证明此方法稳定可靠.
