In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LA...In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.展开更多
This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. A...This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.展开更多
The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are inv...The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.展开更多
A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital c...A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.展开更多
--The solar photovoltaic （PV） module output voltage changes according to the variation of light intensity and temperature. This paper presents the implementation of an automatic digital controller of a DC-DC boost c...--The solar photovoltaic （PV） module output voltage changes according to the variation of light intensity and temperature. This paper presents the implementation of an automatic digital controller of a DC-DC boost converter without batteries for a solar cell module by using a peripheral interface controller, which forms a closed loop, to control the ON-OFF period of the switching pulse. The output of DC-DC converter is maintained by automatically increasing or decreasing the pulse width. To produce the pulse width modulation （PWM）, the microcontroller is programmed according to the required duty cycle for the power switch. The PWM ON period is increased with the decrease in the PV voltage and vice-versa. The input voltage to the inverter is maintained constantly and is converted into an AC signal by using the metal-oxide-semiconductor field effect transistor （MOSFET） H-bridge operated in the sinusoidal pulse width modulation mode by using a PIC （peripheral interface controller） microcontroller. The generated AC signal can be connected to the AC grid or to the AC load. The simulated results by using Proteus 8 and hardware implemented results verify the effectiveness of the proposed controller.展开更多
The digital measurement and processing is an important direction in the measurement and control field. The quantization error widely existing in the digital processing is always the decisive factor that restricts the ...The digital measurement and processing is an important direction in the measurement and control field. The quantization error widely existing in the digital processing is always the decisive factor that restricts the development and applications of the digital technology. In this paper, we find that the stability of the digital quantization system is obviously better than the quantization resolution. The application of a border effect in the digital quantization can greatly improve the accuracy of digital processing. Its effective precision has nothing to do with the number of quantization bits, which is only related to the stability of the quantization system. The high precision measurement results obtained in the low level quantization system with high sampling rate have an important application value for the progress in the digital measurement and processing field.展开更多
A cueing wideband digital Electronic Warfare （EW） receiver is presented. The proposed receiver, which is to measure the instantaneous frequency and bandwidth of the intercept short-duration pulse radar signals that ...A cueing wideband digital Electronic Warfare （EW） receiver is presented. The proposed receiver, which is to measure the instantaneous frequency and bandwidth of the intercept short-duration pulse radar signals that cue and match the corresponding ones, meets the requirements of good sensitivity and dynamic range for EW and can save hardware resources greatly as well. In addition, real-time signal processing, which is the main bottleneck for covering a wide instantaneous frequency band for EW receiver, is better solved in the proposed design structure. The highly efficient implementation and good parameter estimation algorithms are proposed as welL Theoretical analysis and experimental results show that this structure is feasible.展开更多
The R-2R resistor ladder is one of the best topologies for implementing compact-sized digital-to-analog converter(DAC)arrays in implantable neuro-stimulators.However,it has a limited resolution and considerable inter-...The R-2R resistor ladder is one of the best topologies for implementing compact-sized digital-to-analog converter(DAC)arrays in implantable neuro-stimulators.However,it has a limited resolution and considerable inter-channel variation due to component mismatches.To avoid losing analog information,we present sub-radix-2 DAC implemented by the R-βR resistor ladder in this paper.The digital successive approximation register(DSAR)algorithm corrects the transfer function of DACs based on their actual bit weights.Furthermore,a low-cost in situ adaptive bit-weight calibration(ABC)algorithm drives the analog output error between two DACs to zero by adjusting their bit weights automatically.The simulation results show that the proposed algorithm can calibrate the non-linear transfer function of each DAC and the gain error among multiple channels in the background.展开更多
In this article,radiation effects and annealing characteristics of a bipolar analog-to-digital converter(ADC) are investigated in different biases and dose rates.The results show that ADC is sensitive to both the bias...In this article,radiation effects and annealing characteristics of a bipolar analog-to-digital converter(ADC) are investigated in different biases and dose rates.The results show that ADC is sensitive to both the bias and dose rate. Under high-dose-rate irradiation,the ADC functions well,while under low-dose-rate irradiation,the parameters of ADC change obviously at low dose level,and the damage is significant at zero bias.Combining the fringing field with the space charge model,the underlying mechanism for this response is discussed.展开更多
The relationship between the hardware requirement of digital down converters（DDCs）in ultra-low symbol rate receivers and the word length is studied.Through analyzing the impact of word length selection to the system...The relationship between the hardware requirement of digital down converters（DDCs）in ultra-low symbol rate receivers and the word length is studied.Through analyzing the impact of word length selection to the system performance,a modified scheme is presented to decline the resource consumption without too much degradation on the signal to noise ratio（SNR）.Theoretical analysis and numerical results demonstrate that compared to the traditional design,the proposed scheme could save dozens of memory resources.The scheme also includes some selectable parameters to achieve desired performance in various circumstances.Different from previous work in DDCs that concentrates mostly on the structure design,this paper considers special applications such as ultra-low symbol rate receivers.展开更多
基金Supported by National Natural Science Foundation of China (No. 10405023)Knowledge Innovation Program of The Chinese Academy of Sciences (KJCX2-YW-N27)
文摘In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.
基金supported in part by the National Natural Science Foundation of China under Grant No.61006027the New Century Excellent Talents Program of the Ministry of Education of China under Grant No.NCET-10-0297the Fundamental Research Funds for Central Universities under Grant No.ZYGX2012J003
文摘This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.
基金supported by the National Natural Science Foundation of China (Grant No. 11205038)the China Postdoctoral Science Foundation (Grant No. 2012M510951)
文摘The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.
文摘A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.
文摘--The solar photovoltaic （PV） module output voltage changes according to the variation of light intensity and temperature. This paper presents the implementation of an automatic digital controller of a DC-DC boost converter without batteries for a solar cell module by using a peripheral interface controller, which forms a closed loop, to control the ON-OFF period of the switching pulse. The output of DC-DC converter is maintained by automatically increasing or decreasing the pulse width. To produce the pulse width modulation （PWM）, the microcontroller is programmed according to the required duty cycle for the power switch. The PWM ON period is increased with the decrease in the PV voltage and vice-versa. The input voltage to the inverter is maintained constantly and is converted into an AC signal by using the metal-oxide-semiconductor field effect transistor （MOSFET） H-bridge operated in the sinusoidal pulse width modulation mode by using a PIC （peripheral interface controller） microcontroller. The generated AC signal can be connected to the AC grid or to the AC load. The simulated results by using Proteus 8 and hardware implemented results verify the effectiveness of the proposed controller.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.10978017 and 61201288)Shaanxi Natural Science Foundation Research Plan Projects,China(Grant No.2014JM2-6128)Shaanxi Major Technological Achievements Transformation and Guidance Special Projects,China(Grant No.2015KTCG01-01)
文摘The digital measurement and processing is an important direction in the measurement and control field. The quantization error widely existing in the digital processing is always the decisive factor that restricts the development and applications of the digital technology. In this paper, we find that the stability of the digital quantization system is obviously better than the quantization resolution. The application of a border effect in the digital quantization can greatly improve the accuracy of digital processing. Its effective precision has nothing to do with the number of quantization bits, which is only related to the stability of the quantization system. The high precision measurement results obtained in the low level quantization system with high sampling rate have an important application value for the progress in the digital measurement and processing field.
基金Supported by the National Defense Pre-research Fund of China
文摘A cueing wideband digital Electronic Warfare （EW） receiver is presented. The proposed receiver, which is to measure the instantaneous frequency and bandwidth of the intercept short-duration pulse radar signals that cue and match the corresponding ones, meets the requirements of good sensitivity and dynamic range for EW and can save hardware resources greatly as well. In addition, real-time signal processing, which is the main bottleneck for covering a wide instantaneous frequency band for EW receiver, is better solved in the proposed design structure. The highly efficient implementation and good parameter estimation algorithms are proposed as welL Theoretical analysis and experimental results show that this structure is feasible.
基金supported by the Shanghai Municipal of Science and Technology Project under Grant No.20JC1419500the Open Research Projects of Zhejiang Lab under Grant No.2021MC0AB06.
文摘The R-2R resistor ladder is one of the best topologies for implementing compact-sized digital-to-analog converter(DAC)arrays in implantable neuro-stimulators.However,it has a limited resolution and considerable inter-channel variation due to component mismatches.To avoid losing analog information,we present sub-radix-2 DAC implemented by the R-βR resistor ladder in this paper.The digital successive approximation register(DSAR)algorithm corrects the transfer function of DACs based on their actual bit weights.Furthermore,a low-cost in situ adaptive bit-weight calibration(ABC)algorithm drives the analog output error between two DACs to zero by adjusting their bit weights automatically.The simulation results show that the proposed algorithm can calibrate the non-linear transfer function of each DAC and the gain error among multiple channels in the background.
文摘In this article,radiation effects and annealing characteristics of a bipolar analog-to-digital converter(ADC) are investigated in different biases and dose rates.The results show that ADC is sensitive to both the bias and dose rate. Under high-dose-rate irradiation,the ADC functions well,while under low-dose-rate irradiation,the parameters of ADC change obviously at low dose level,and the damage is significant at zero bias.Combining the fringing field with the space charge model,the underlying mechanism for this response is discussed.
基金Supported by the National Natural Science Foundation of China(60972018)
文摘The relationship between the hardware requirement of digital down converters（DDCs）in ultra-low symbol rate receivers and the word length is studied.Through analyzing the impact of word length selection to the system performance,a modified scheme is presented to decline the resource consumption without too much degradation on the signal to noise ratio（SNR）.Theoretical analysis and numerical results demonstrate that compared to the traditional design,the proposed scheme could save dozens of memory resources.The scheme also includes some selectable parameters to achieve desired performance in various circumstances.Different from previous work in DDCs that concentrates mostly on the structure design,this paper considers special applications such as ultra-low symbol rate receivers.
