The need for wide-band clock and data recovery （CDR） circuits is discussed. A 2 Gbps to 12 Gbps continuous-rate CDR circuit employing a multi-mode voltage-control oscillator （VCO）, a frequency detector, and a phas...The need for wide-band clock and data recovery （CDR） circuits is discussed. A 2 Gbps to 12 Gbps continuous-rate CDR circuit employing a multi-mode voltage-control oscillator （VCO）, a frequency detector, and a phase detector （FD＆PD） is described. A new automatic frequency band selection （FBS） without external reference clock is proposed to select the appropriate mode and also solve the instability problem when the circuit is powering on. The multi-mode VCO and FD/PD circuits which can operate at full-rate and half-rate modes facilitate CDR with six operation modes. The proposed CDR structure has been modeled with MATLAB and the simulated results validate its feasibility.展开更多
In this paper, a phase interpolator clock and data recovery （CDR） with low-voltage current mode logic （CML） latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low...In this paper, a phase interpolator clock and data recovery （CDR） with low-voltage current mode logic （CML） latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low supply voltage. And the original swing of the differential inputs and outputs is less than that of the CMOS logic. The power supply voltage is 1.2 V, and the static current consumption is about 20 mA. In this phase interpolator CDR, the charge pump and loop filter are replaced by a digital filter. And this structure offers the benefits of increased system stability and faster acquisition.展开更多
基金supported by the Hubei Natural Science Foundation of China underGrant No. 2010CDB02706the Fundamental Research Funds for the Central Universities under Grant No. C2009Q060
文摘The need for wide-band clock and data recovery （CDR） circuits is discussed. A 2 Gbps to 12 Gbps continuous-rate CDR circuit employing a multi-mode voltage-control oscillator （VCO）, a frequency detector, and a phase detector （FD＆PD） is described. A new automatic frequency band selection （FBS） without external reference clock is proposed to select the appropriate mode and also solve the instability problem when the circuit is powering on. The multi-mode VCO and FD/PD circuits which can operate at full-rate and half-rate modes facilitate CDR with six operation modes. The proposed CDR structure has been modeled with MATLAB and the simulated results validate its feasibility.
基金supported by the Fundamental Research Funds for the Central Universities under Grant No.2009JBM001
文摘In this paper, a phase interpolator clock and data recovery （CDR） with low-voltage current mode logic （CML） latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low supply voltage. And the original swing of the differential inputs and outputs is less than that of the CMOS logic. The power supply voltage is 1.2 V, and the static current consumption is about 20 mA. In this phase interpolator CDR, the charge pump and loop filter are replaced by a digital filter. And this structure offers the benefits of increased system stability and faster acquisition.
