A DC DC buck converter c on trolled by naturally sampled, constant frequency PWM is considered. The existe nce of chaotic solutions and the output performance of the system under differen t circuit parameters are s...A DC DC buck converter c on trolled by naturally sampled, constant frequency PWM is considered. The existe nce of chaotic solutions and the output performance of the system under differen t circuit parameters are studied. The transforming pattern of system behavior fr om steady state to chaotic is discovered by the cascades of period doubling bi furcation and the cascades of periodic orbit in V I phase space. Accordingl y, it is validated that change of values of the circuit parameters may lead DC DC converter to chaotic motion. Performances of the output ripples fro m steady state to chaotic are analyzed in time and frequency domains respective ly. Some important conclusions are helpful for opt imization design of DC DC converter.展开更多
采用0.35μm 18 V DPTM BCD工艺技术给出电流模降压型DC-DC转换器的功率级设计,该功率级可以输出3A负载电流,转换效率可达到94.5%。主要针对转换器中核心部分功率级进行设计,其中包括同步开关功率晶体管设计、片上电感电流检测电路、功...采用0.35μm 18 V DPTM BCD工艺技术给出电流模降压型DC-DC转换器的功率级设计,该功率级可以输出3A负载电流,转换效率可达到94.5%。主要针对转换器中核心部分功率级进行设计,其中包括同步开关功率晶体管设计、片上电感电流检测电路、功率晶体管驱动电路设计以及功率级的版图设计考虑,最后给出了该功率级设计的测试结果 。展开更多
为了降低CMOS降压型DC-DC变换器的功耗,提出了一种双延迟线结构数字脉宽调制器DPWM(Digital Pulse Width Modulator)设计。该DPWM架构由双延迟线组成,可以降低功耗并通过改变分辨率来提高纹波电压。通过使用8位和16位延迟线实现了虚拟12...为了降低CMOS降压型DC-DC变换器的功耗,提出了一种双延迟线结构数字脉宽调制器DPWM(Digital Pulse Width Modulator)设计。该DPWM架构由双延迟线组成,可以降低功耗并通过改变分辨率来提高纹波电压。通过使用8位和16位延迟线实现了虚拟128位延迟线,并提出了相应的DPWM控制算法。基于180 nm TSMC CMOS工艺,采用Cadence软件进行仿真分析。仿真和实际测量结果表明,提出的双延迟链DPWM功耗为1.18μW,纹波电压为10.4 m V。工作频率100 k Hz时在4 m A^10 m A的负载电流范围内,与传统转换器相比,具有所提出DPWM的DC-DC变换器实现了较高的峰值效率92.8%,且有效面积较小。展开更多
文摘A DC DC buck converter c on trolled by naturally sampled, constant frequency PWM is considered. The existe nce of chaotic solutions and the output performance of the system under differen t circuit parameters are studied. The transforming pattern of system behavior fr om steady state to chaotic is discovered by the cascades of period doubling bi furcation and the cascades of periodic orbit in V I phase space. Accordingl y, it is validated that change of values of the circuit parameters may lead DC DC converter to chaotic motion. Performances of the output ripples fro m steady state to chaotic are analyzed in time and frequency domains respective ly. Some important conclusions are helpful for opt imization design of DC DC converter.
文摘为了降低CMOS降压型DC-DC变换器的功耗,提出了一种双延迟线结构数字脉宽调制器DPWM(Digital Pulse Width Modulator)设计。该DPWM架构由双延迟线组成,可以降低功耗并通过改变分辨率来提高纹波电压。通过使用8位和16位延迟线实现了虚拟128位延迟线,并提出了相应的DPWM控制算法。基于180 nm TSMC CMOS工艺,采用Cadence软件进行仿真分析。仿真和实际测量结果表明,提出的双延迟链DPWM功耗为1.18μW,纹波电压为10.4 m V。工作频率100 k Hz时在4 m A^10 m A的负载电流范围内,与传统转换器相比,具有所提出DPWM的DC-DC变换器实现了较高的峰值效率92.8%,且有效面积较小。
