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High pressure CMP with low stress polishing
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作者 Hiroshi Ishizuka Sung James C. +2 位作者 Marehito Aoki Haedo Jeong Sung Michael 《金刚石与磨料磨具工程》 CAS 北大核心 2008年第S1期119-125,129,共8页
Low stress polishing is required for the manufacture of advanced integrated circuits(IC) with node sizes of 45 nm and smaller.However,the CMP community achieved the low stress by reducing the down force that press the... Low stress polishing is required for the manufacture of advanced integrated circuits(IC) with node sizes of 45 nm and smaller.However,the CMP community achieved the low stress by reducing the down force that press the wafer against a rotating pad.The reduced down force also decrease the removal rate of the wafer. As a result,the productivity suffers.In order to cope with this problem,an electrical potential is applied to the copper layer during polishing,in this case,the chemical oxidation is accelearated and hence the removal rate. Alternatively,the rotating pad must be softened to minimize the defects of wafers caused by CMP. In this research,we report a simpler solution to achieve low stress polishing without investing in new equipment and in developing new pad materials.The conventional CMP is proceeded by dressing the pad with a PCD dresser that can form 10×more asperities on the pad surface.The fluffy surface can then polish delicate IC without using the brutal force.As a result,the removal rate of wafers can be maintained without causing defectivity on the IC layer. 展开更多
关键词 IC CMP eCMP PCD DRESSER Moore’s Law 32nm node
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