采用噪声抵消及多重功耗优化技术,提出了一种超宽带低噪声低功耗放大器。它主要包括采用RL网络的共栅输入级、电流复用型噪声抵消级、放大输出级以及偏置电路4个部分。验证结果表明,该放大器,在2 GHz^6 GHz频带内,增益(S21)可以在14 d ...采用噪声抵消及多重功耗优化技术,提出了一种超宽带低噪声低功耗放大器。它主要包括采用RL网络的共栅输入级、电流复用型噪声抵消级、放大输出级以及偏置电路4个部分。验证结果表明,该放大器,在2 GHz^6 GHz频带内,增益(S21)可以在14 d B以上;输入回波损耗(S11)小于-10 d B;输出回波损耗(S22)小于-25 d B;噪声系数(NF)小于3.2 d B;在3.8V的工作电压下,功耗仅为14 m W。展开更多
In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave （mmW） band is designed and implemented in 90nm CMOS technology. The 60GHz ...In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave （mmW） band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier （LNA） with inter-stage peaking technique, a single- balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.1lad standard for next generation high speed Wi- Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.SdBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply.展开更多
文摘采用噪声抵消及多重功耗优化技术,提出了一种超宽带低噪声低功耗放大器。它主要包括采用RL网络的共栅输入级、电流复用型噪声抵消级、放大输出级以及偏置电路4个部分。验证结果表明,该放大器,在2 GHz^6 GHz频带内,增益(S21)可以在14 d B以上;输入回波损耗(S11)小于-10 d B;输出回波损耗(S22)小于-25 d B;噪声系数(NF)小于3.2 d B;在3.8V的工作电压下,功耗仅为14 m W。
基金supported by National 973 Program of China 2010CB327404National 863 Program of China 2011AA010202+2 种基金National Science and Technology Major Project of China 2012ZX03004004National Natural Science Foundation of China under grants 61101001,and 61204026Tsinghua University Initiative Scientific Research Program
文摘In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave （mmW） band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier （LNA） with inter-stage peaking technique, a single- balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.1lad standard for next generation high speed Wi- Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.SdBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply.
