In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product uni...In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.展开更多
A new multi-species particle swarm optimization with a two-level hierarchical topology and the orthogonal learning strategy(OMSPSO) is proposed, which enhances the global search ability of particles and increases thei...A new multi-species particle swarm optimization with a two-level hierarchical topology and the orthogonal learning strategy(OMSPSO) is proposed, which enhances the global search ability of particles and increases their convergence rates. The numerical results on 10 benchmark functions demonstrated the effectiveness of our proposed algorithm. Then, the proposed algorithm is presented to design a butterfly-shaped microstrip patch antenna. Combined with the HFSS solver, a butterfly-shaped patch antenna with a bandwidth of about 40.1% is designed by using the proposed OMSPSO. The return loss of the butterfly-shaped antenna is greater than 10 d B between 4.15 and 6.36 GHz. The antenna can serve simultaneously for the high-speed wireless computer networks(5.15–5.35 GHz) and the RFID systems(5.8 GHz).展开更多
文摘In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.
基金Project(61105067)supported by the National Natural Science Foundation of China
文摘A new multi-species particle swarm optimization with a two-level hierarchical topology and the orthogonal learning strategy(OMSPSO) is proposed, which enhances the global search ability of particles and increases their convergence rates. The numerical results on 10 benchmark functions demonstrated the effectiveness of our proposed algorithm. Then, the proposed algorithm is presented to design a butterfly-shaped microstrip patch antenna. Combined with the HFSS solver, a butterfly-shaped patch antenna with a bandwidth of about 40.1% is designed by using the proposed OMSPSO. The return loss of the butterfly-shaped antenna is greater than 10 d B between 4.15 and 6.36 GHz. The antenna can serve simultaneously for the high-speed wireless computer networks(5.15–5.35 GHz) and the RFID systems(5.8 GHz).
