基础数学函数库是计算机系统非常关键的软件模块,然而国产申威平台上的长向量超越函数只能依靠循环调用系统标量函数来间接实现,该方法无法充分发挥申威平台SIMD扩展部件的计算性能。为了有效解决此问题,实现了申威平台基于SIMD扩展部...基础数学函数库是计算机系统非常关键的软件模块,然而国产申威平台上的长向量超越函数只能依靠循环调用系统标量函数来间接实现,该方法无法充分发挥申威平台SIMD扩展部件的计算性能。为了有效解决此问题,实现了申威平台基于SIMD扩展部件底层优化的长向量超越函数,提出了浮点计算融合算法,解决了两分支结构算法难以向量化的问题;提出了基于Estrin算法动态分组的大阶数多项式实现方法,提高了多项式汇编计算的流水性能。这是在国产申威平台上首次实现长向量超越函数库,提供的函数接口包含三角函数、反三角函数、对数函数、指数函数等。实验结果表明,双精度版本最大误差控制在3.5ULP(unit in the last place)以下,单精度版本最大误差控制在0.5ULP以下,该性能与申威平台直接循环调用系统标量函数相比有显著提高,平均加速比为3.71。展开更多
In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product uni...In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.展开更多
文摘基础数学函数库是计算机系统非常关键的软件模块,然而国产申威平台上的长向量超越函数只能依靠循环调用系统标量函数来间接实现,该方法无法充分发挥申威平台SIMD扩展部件的计算性能。为了有效解决此问题,实现了申威平台基于SIMD扩展部件底层优化的长向量超越函数,提出了浮点计算融合算法,解决了两分支结构算法难以向量化的问题;提出了基于Estrin算法动态分组的大阶数多项式实现方法,提高了多项式汇编计算的流水性能。这是在国产申威平台上首次实现长向量超越函数库,提供的函数接口包含三角函数、反三角函数、对数函数、指数函数等。实验结果表明,双精度版本最大误差控制在3.5ULP(unit in the last place)以下,单精度版本最大误差控制在0.5ULP以下,该性能与申威平台直接循环调用系统标量函数相比有显著提高,平均加速比为3.71。
文摘In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.
