Aim To design an ASIC based on CORDIC(coordinate rotations digital computer) to meet the requirement of coordinate conversion in high speed radar signal processing. Methods A new pipeline CORDIC architecture easi...Aim To design an ASIC based on CORDIC(coordinate rotations digital computer) to meet the requirement of coordinate conversion in high speed radar signal processing. Methods A new pipeline CORDIC architecture easily realized in VLSI was introduced. Results and Conclusion The results of hardware simulation with FPGA show that the pipeline CORDIC architecture meets the requirement.展开更多
A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor shari...A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.展开更多
It is important for the safety of transmission system to accurately calculate single-phase earth fault current distribution.Features of double sided elimination method were illustrated.Quantitative calculation of sing...It is important for the safety of transmission system to accurately calculate single-phase earth fault current distribution.Features of double sided elimination method were illustrated.Quantitative calculation of single-phase earth fault current distribution and case verification were accomplished by using the loop method.Influences of some factors,such as single-phase earth fault location and ground resistance of poles,on short-circuit current distribution were discussed.Results show that:1) results of the loop method conform to those of double sided elimination method;2) the fault location hardly influences macro-distribution of short-circuit current.However,current near fault location is evidently influenced;and 3) the short-circuit current distribution is not so sensitive to the ground resistance of poles.展开更多
文摘Aim To design an ASIC based on CORDIC(coordinate rotations digital computer) to meet the requirement of coordinate conversion in high speed radar signal processing. Methods A new pipeline CORDIC architecture easily realized in VLSI was introduced. Results and Conclusion The results of hardware simulation with FPGA show that the pipeline CORDIC architecture meets the requirement.
基金supported by the Major National Science & Technology Program of China under Grant No.2012ZX03004004-002National High Technology Research and Development Program of China under Grant No. 2013AA014302
文摘A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.
文摘It is important for the safety of transmission system to accurately calculate single-phase earth fault current distribution.Features of double sided elimination method were illustrated.Quantitative calculation of single-phase earth fault current distribution and case verification were accomplished by using the loop method.Influences of some factors,such as single-phase earth fault location and ground resistance of poles,on short-circuit current distribution were discussed.Results show that:1) results of the loop method conform to those of double sided elimination method;2) the fault location hardly influences macro-distribution of short-circuit current.However,current near fault location is evidently influenced;and 3) the short-circuit current distribution is not so sensitive to the ground resistance of poles.
