It is well-known that the IMC-PID controller tuning gives fast and improved set point response but slow disturbance rejection. A modification has been proposed in IMC-PID tuning rule for the improved disturbance rejec...It is well-known that the IMC-PID controller tuning gives fast and improved set point response but slow disturbance rejection. A modification has been proposed in IMC-PID tuning rule for the improved disturbance rejection. For the modified IMC-PID tuning rule, a method has been developed to obtain the IMC-PID setting in closed-loop mode without acquiring detailed information of the process. The proposed method is based on the closed-loop step set point experiment using a proportional only controller with gain K_(c0). It is the direct approach to find the PID controller setting similar to classical Ziegler-Nichols closed-loop method. Based on simulations of a wide range of first-order with delay processes, a simple correlation has been derived to obtain the modified IMC-PID controller settings from closed-loop experiment. In this method, controller gain is a function of the overshoot obtained in the closed loop set point experiment. The integral and derivative time is mainly a function of the time to reach the first peak(overshoot). Simulation has been conducted for the broad class of processes and the controllers were tuned to have the same degree of robustness by measuring the maximum sensitivity, Ms, in order to obtain a reasonable comparison. The PID controller settings obtained in the proposed tuning method show better performance and robustness with other two-step tuning methods for the broad class of processes. It has also been applied to temperature control loop in distillation column model. The result has been compared to the open loop tuning method where it gives robust and fast response.展开更多
On augmentation of past work, an effective Wiener filter and its application for noise suppression combined with a formed CORDIC based FFT/IFFT processor with improved speed were executed. The pipelined methodology wa...On augmentation of past work, an effective Wiener filter and its application for noise suppression combined with a formed CORDIC based FFT/IFFT processor with improved speed were executed. The pipelined methodology was embraced for expanding the execution of the system. The proposed Wiener filter was planned in such an approach to evacuate the iteration issues in ordinary Wiener filter. The division process was supplanted by a productive inverse and multiplication process in the proposed design. An enhanced design for matrix inverse with reduced computation complexity was executed. The wide-ranging framework processing was focused around IEEE-754 standard single precision floating point numbers. The Wiener filter and the entire system design was integrated and actualized on VIRTEX 5 FPGA stage and re-enacted to approve the results in Xilinx ISE 13.4. The results show that a productive decrease in power and area is developed by adjusting the proposed technique for speech signal noise degradation with latency of n/2 clock cycles and substantial throughput result per every 12 clock cycles for n-bit precision. The execution of proposed design is exposed to be 31.35% more effective than that of prevailing strategies.展开更多
基金the support provided by King Abdulaziz City for Science and Technology (KACST) through the Science & Technology Unit at King Fahd University of PetroleumMinerals (KFUPM) for funding this work through project number 11-ENE1643-04 as part of the Notional Science Technology and Innovation Plan
文摘It is well-known that the IMC-PID controller tuning gives fast and improved set point response but slow disturbance rejection. A modification has been proposed in IMC-PID tuning rule for the improved disturbance rejection. For the modified IMC-PID tuning rule, a method has been developed to obtain the IMC-PID setting in closed-loop mode without acquiring detailed information of the process. The proposed method is based on the closed-loop step set point experiment using a proportional only controller with gain K_(c0). It is the direct approach to find the PID controller setting similar to classical Ziegler-Nichols closed-loop method. Based on simulations of a wide range of first-order with delay processes, a simple correlation has been derived to obtain the modified IMC-PID controller settings from closed-loop experiment. In this method, controller gain is a function of the overshoot obtained in the closed loop set point experiment. The integral and derivative time is mainly a function of the time to reach the first peak(overshoot). Simulation has been conducted for the broad class of processes and the controllers were tuned to have the same degree of robustness by measuring the maximum sensitivity, Ms, in order to obtain a reasonable comparison. The PID controller settings obtained in the proposed tuning method show better performance and robustness with other two-step tuning methods for the broad class of processes. It has also been applied to temperature control loop in distillation column model. The result has been compared to the open loop tuning method where it gives robust and fast response.
文摘On augmentation of past work, an effective Wiener filter and its application for noise suppression combined with a formed CORDIC based FFT/IFFT processor with improved speed were executed. The pipelined methodology was embraced for expanding the execution of the system. The proposed Wiener filter was planned in such an approach to evacuate the iteration issues in ordinary Wiener filter. The division process was supplanted by a productive inverse and multiplication process in the proposed design. An enhanced design for matrix inverse with reduced computation complexity was executed. The wide-ranging framework processing was focused around IEEE-754 standard single precision floating point numbers. The Wiener filter and the entire system design was integrated and actualized on VIRTEX 5 FPGA stage and re-enacted to approve the results in Xilinx ISE 13.4. The results show that a productive decrease in power and area is developed by adjusting the proposed technique for speech signal noise degradation with latency of n/2 clock cycles and substantial throughput result per every 12 clock cycles for n-bit precision. The execution of proposed design is exposed to be 31.35% more effective than that of prevailing strategies.
