Wireless sensor-actuator networks can bring flexibility to smart home.We design and develop a smart home prototype using wireless sensor-actuator network technology to realize environmental sensing and the control of ...Wireless sensor-actuator networks can bring flexibility to smart home.We design and develop a smart home prototype using wireless sensor-actuator network technology to realize environmental sensing and the control of electric appliances.The basic motivation of our solution is to utilize the collaboration among a mass of low-cost sensor nodes and actuator nodes to make life convenient.To achieve it,we design a novel system architecture with assembled component modules.In particular,we address some key technical challenges:1) Field-Programmable Gate Array (FPGA) Implementation of Adaptive Differential Pulse Code Modulation (ADPCM) for audio data;2) FPGA Implementation of Lempel Ziv Storer Szymanski (LZSS) for bulk data;3) combination of complex control logic.Finally,a set of experiments are presented to evaluate the performance of our solution.展开更多
Abstract： This work proposes a Field Programmable Gate Array （FPGA）-oriented architecture for the IEEE 802.11 Distributed Coordination Function （DCF） transceiver. We describe the functional blocks carrying out th...Abstract： This work proposes a Field Programmable Gate Array （FPGA）-oriented architecture for the IEEE 802.11 Distributed Coordination Function （DCF） transceiver. We describe the functional blocks carrying out the Carrier Sense Multiple Accesses with Collision Avoidance （CSMA/CA）, develop the interfaces to the application layer and the physical layer, and implement it on FPGA devices by utilizing Very-high-speed-integrated-circuit Hardware Description Language （VHDL）.展开更多
A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchr...A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.展开更多
Abstract： Real-time digital service and mul- timedia service upstream transmission in Dig- ital Signal Processing （DSP）-based Orthogo- nal Frequency Division Multiplexing-Passive Optical Network （OFDM-PON） is exp...Abstract： Real-time digital service and mul- timedia service upstream transmission in Dig- ital Signal Processing （DSP）-based Orthogo- nal Frequency Division Multiplexing-Passive Optical Network （OFDM-PON） is experimen- tally demonstrated with Centralised Light Sou- rce （CLS） configuration in this paper. After transmitted over 25 km Standard Single Mode Fibre （SSMF） with -16.5 dBm optical power at receiver, the Bit Error Rate （BER） is 9.5 ×10^-11. The implementations of digital domain up-conversion and down-conversion based on Field Programmable Gate Array （FPGA） are int- roduced, which can reduce the cost of In-ph- ase and Quadrature （IQ） radio frequency mix- ers utilised at transmitter and receiver. A car- rier synchronization algorithm is implemented for compensating carrier offset. A channel eq- ualization algorithm is adopted for compen- sating the damage of channel. A new structure of Frequency Synchronization Unit （FSU） des- igned in FPGA is also proposed to cope with the frequency shifting at receiver.展开更多
基金supported by the Natural Science Foundation of China under Grant No.61070206,No.61070205and No.60833009the National973Project of China under Grant No.2011CB302701+2 种基金the program of New Century Excellent Talents in University of China under Grant No.NCET-080737the Beijing National Natural Science Foundation under Grant No.4092030the Cosponsored Project of Beijing Committee of Education
文摘Wireless sensor-actuator networks can bring flexibility to smart home.We design and develop a smart home prototype using wireless sensor-actuator network technology to realize environmental sensing and the control of electric appliances.The basic motivation of our solution is to utilize the collaboration among a mass of low-cost sensor nodes and actuator nodes to make life convenient.To achieve it,we design a novel system architecture with assembled component modules.In particular,we address some key technical challenges:1) Field-Programmable Gate Array (FPGA) Implementation of Adaptive Differential Pulse Code Modulation (ADPCM) for audio data;2) FPGA Implementation of Lempel Ziv Storer Szymanski (LZSS) for bulk data;3) combination of complex control logic.Finally,a set of experiments are presented to evaluate the performance of our solution.
基金the National Natural Science Foundation of China
文摘Abstract： This work proposes a Field Programmable Gate Array （FPGA）-oriented architecture for the IEEE 802.11 Distributed Coordination Function （DCF） transceiver. We describe the functional blocks carrying out the Carrier Sense Multiple Accesses with Collision Avoidance （CSMA/CA）, develop the interfaces to the application layer and the physical layer, and implement it on FPGA devices by utilizing Very-high-speed-integrated-circuit Hardware Description Language （VHDL）.
基金the Natural Science Foundation of Hubei Province (No.2005ABA301)
文摘A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.
基金ACKNOWLEDGEMENT This work was supported in part by the Na- tional Natural Science Foundation of China under Grants No. 61271192, No. 60932004 the National High Technology Research and Development of China （863 Program） under Grant No. 2013AA013401 and the National Basic Research Program of China under Grant No. 2013CB329204.
文摘Abstract： Real-time digital service and mul- timedia service upstream transmission in Dig- ital Signal Processing （DSP）-based Orthogo- nal Frequency Division Multiplexing-Passive Optical Network （OFDM-PON） is experimen- tally demonstrated with Centralised Light Sou- rce （CLS） configuration in this paper. After transmitted over 25 km Standard Single Mode Fibre （SSMF） with -16.5 dBm optical power at receiver, the Bit Error Rate （BER） is 9.5 ×10^-11. The implementations of digital domain up-conversion and down-conversion based on Field Programmable Gate Array （FPGA） are int- roduced, which can reduce the cost of In-ph- ase and Quadrature （IQ） radio frequency mix- ers utilised at transmitter and receiver. A car- rier synchronization algorithm is implemented for compensating carrier offset. A channel eq- ualization algorithm is adopted for compen- sating the damage of channel. A new structure of Frequency Synchronization Unit （FSU） des- igned in FPGA is also proposed to cope with the frequency shifting at receiver.
