Due to the limited scenes that synthetic aperture radar(SAR)satellites can detect,the full-track utilization rate is not high.Because of the computing and storage limitation of one satellite,it is difficult to process...Due to the limited scenes that synthetic aperture radar(SAR)satellites can detect,the full-track utilization rate is not high.Because of the computing and storage limitation of one satellite,it is difficult to process large amounts of data of spaceborne synthetic aperture radars.It is proposed to use a new method of networked satellite data processing for improving the efficiency of data processing.A multi-satellite distributed SAR real-time processing method based on Chirp Scaling(CS)imaging algorithm is studied in this paper,and a distributed data processing system is built with field programmable gate array(FPGA)chips as the kernel.Different from the traditional CS algorithm processing,the system divides data processing into three stages.The computing tasks are reasonably allocated to different data processing units(i.e.,satellites)in each stage.The method effectively saves computing and storage resources of satellites,improves the utilization rate of a single satellite,and shortens the data processing time.Gaofen-3(GF-3)satellite SAR raw data is processed by the system,with the performance of the method verified.展开更多
A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral com...A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.展开更多
As semiconductor technologies have been shrinking,the speed of circuits,integration density,and the number of I/O interfaces have been significantly increasing.As a consequence,electromagnetic emanation(EME)becomes a ...As semiconductor technologies have been shrinking,the speed of circuits,integration density,and the number of I/O interfaces have been significantly increasing.As a consequence,electromagnetic emanation(EME)becomes a critical issue in digital system designs.Electronic devices must meet electromagnetic compatibility(EMC)requirements to ensure that they operate properly,and safely without interference.I/O buffers consume high currents when they operate.The bonding wires,and lead frames are long enough to play as efficient antennas to radiate electromagnetic interference(EMI).Therefore,I/O switching activities significantly contribute to the EMI.In this paper,we evaluate and analyze the impact of I/O switching activities on the EME.We will change the circuit configurations such as the supply voltage for I/O banks,their switching frequency,driving current,and slew rate.Additionally,a trade-off between the switching frequencies and the number of simultaneous switching outputs(SSOs)is also considered in terms of EME.Moreover,we evaluate the electromagnetic emissions that are associated with the different I/O switching patterns.The results show that the electromagnetic emissions associated I/O switching activities depend strongly on their operating parameters and configurations.All the circuit implementations and measurements are carried out on a Xilinx Spartan-3 FPGA.展开更多
基金Project(2017YFC1405600)supported by the National Key R&D Program of ChinaProject(18JK05032)supported by the Scientific Research Project of Education Department of Shaanxi Province,China。
文摘Due to the limited scenes that synthetic aperture radar(SAR)satellites can detect,the full-track utilization rate is not high.Because of the computing and storage limitation of one satellite,it is difficult to process large amounts of data of spaceborne synthetic aperture radars.It is proposed to use a new method of networked satellite data processing for improving the efficiency of data processing.A multi-satellite distributed SAR real-time processing method based on Chirp Scaling(CS)imaging algorithm is studied in this paper,and a distributed data processing system is built with field programmable gate array(FPGA)chips as the kernel.Different from the traditional CS algorithm processing,the system divides data processing into three stages.The computing tasks are reasonably allocated to different data processing units(i.e.,satellites)in each stage.The method effectively saves computing and storage resources of satellites,improves the utilization rate of a single satellite,and shortens the data processing time.Gaofen-3(GF-3)satellite SAR raw data is processed by the system,with the performance of the method verified.
基金Projects(61203308,61309014)supported by the National Natural Science Foundation of China
文摘A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.
基金Project(2018R1D1A1B07043399)supported by Basic Science Research Program through the National Research Foundation,Korea
文摘As semiconductor technologies have been shrinking,the speed of circuits,integration density,and the number of I/O interfaces have been significantly increasing.As a consequence,electromagnetic emanation(EME)becomes a critical issue in digital system designs.Electronic devices must meet electromagnetic compatibility(EMC)requirements to ensure that they operate properly,and safely without interference.I/O buffers consume high currents when they operate.The bonding wires,and lead frames are long enough to play as efficient antennas to radiate electromagnetic interference(EMI).Therefore,I/O switching activities significantly contribute to the EMI.In this paper,we evaluate and analyze the impact of I/O switching activities on the EME.We will change the circuit configurations such as the supply voltage for I/O banks,their switching frequency,driving current,and slew rate.Additionally,a trade-off between the switching frequencies and the number of simultaneous switching outputs(SSOs)is also considered in terms of EME.Moreover,we evaluate the electromagnetic emissions that are associated with the different I/O switching patterns.The results show that the electromagnetic emissions associated I/O switching activities depend strongly on their operating parameters and configurations.All the circuit implementations and measurements are carried out on a Xilinx Spartan-3 FPGA.
