传统磁盘存储设备因其固有的机械特性,已不能满足当前的数据密集型应用程序的需求。基于闪存的固态存储设备(solid state drive,SSD)的出现改善了这种情况,并被广泛用作缓存以降低内存与磁盘之间的性能差距。针对由DRAM和SSD构成的多级...传统磁盘存储设备因其固有的机械特性,已不能满足当前的数据密集型应用程序的需求。基于闪存的固态存储设备(solid state drive,SSD)的出现改善了这种情况,并被广泛用作缓存以降低内存与磁盘之间的性能差距。针对由DRAM和SSD构成的多级缓存,提出了一种可配置的历史信息感知的多级缓存替换策略Charm.Charm允许用户配置应用的访问模式、读写模式等多项内容,并且还可以根据应用对文件的历史访问信息来判断访问模式,从而能够适应访问模式的变化.此外,Charm过滤掉那些只访问一次的数据,将多次访问的热数据缓存至SSD,减少对SSD的写入次数,提升SSD寿命.使用MCsim对Charm与现有的多级缓存替换算法进行了对比测试,在实际的工作负载下,Charm优于其它多级缓存算法.展开更多
半导体技术快速发展,双倍数据速率同步动态随机存取存储器(Double Data Rata Synchronous Dynamic Random Access Memory,DDR SDRAM)的信号完整性问题已成为设计难点。文中提出了一种基于ANSYS软件和IBIS 5.0模型的DDR4 SDRAM信号完整...半导体技术快速发展,双倍数据速率同步动态随机存取存储器(Double Data Rata Synchronous Dynamic Random Access Memory,DDR SDRAM)的信号完整性问题已成为设计难点。文中提出了一种基于ANSYS软件和IBIS 5.0模型的DDR4 SDRAM信号完整性仿真方法。利用IBIS 5.0模型中增加的复合电流(Composite Current)、同步开关输出电流等数据,对DDR4 SDRAM高速电路板的信号完整性进行更准确的仿真分析。仿真结果表明:高速信号在经过印制板走线和器件封装后,信号摆幅和眼图都有明显恶化;在仿真电路的电源上增加去耦电容后,信号抖动和收发端同步开关噪声(Synchronous Switching Noise,SSN)都得到明显改善;在不加去耦电容的情况下,将输入信号由PRBS码换成DBI信号,接收端的同步开关噪声有所改善,器件功耗可以降为原来的一半。展开更多
The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）,...The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）, negative word-line voltage （VinyL） and half-VDD voltage （VHDo） generator. To generate a process voltage temperature （PVT）-insensitive VpWL and VNWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a VOWL regulator and a VNWL charge pump were proposed for a small-area and low-power design. The proposed VpwL regulator can provide a large driving current with a small area since it regulates an input voltage （VCI） from 2.5 to 3.3 V. The VmvL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to VNWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.展开更多
文摘传统磁盘存储设备因其固有的机械特性,已不能满足当前的数据密集型应用程序的需求。基于闪存的固态存储设备(solid state drive,SSD)的出现改善了这种情况,并被广泛用作缓存以降低内存与磁盘之间的性能差距。针对由DRAM和SSD构成的多级缓存,提出了一种可配置的历史信息感知的多级缓存替换策略Charm.Charm允许用户配置应用的访问模式、读写模式等多项内容,并且还可以根据应用对文件的历史访问信息来判断访问模式,从而能够适应访问模式的变化.此外,Charm过滤掉那些只访问一次的数据,将多次访问的热数据缓存至SSD,减少对SSD的写入次数,提升SSD寿命.使用MCsim对Charm与现有的多级缓存替换算法进行了对比测试,在实际的工作负载下,Charm优于其它多级缓存算法.
基金supported by the Second Stage of Brain Korea 21 Projectsfinancially supported by Changwon National University in 2011-2013
文摘The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）, negative word-line voltage （VinyL） and half-VDD voltage （VHDo） generator. To generate a process voltage temperature （PVT）-insensitive VpWL and VNWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a VOWL regulator and a VNWL charge pump were proposed for a small-area and low-power design. The proposed VpwL regulator can provide a large driving current with a small area since it regulates an input voltage （VCI） from 2.5 to 3.3 V. The VmvL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to VNWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.
