Due to the advantages of low cost,fast response and pollution resistance,digital hydraulic pump/motor can replace conventional variable hydraulic pump/motor in many application fields.However,digital hydraulic compone...Due to the advantages of low cost,fast response and pollution resistance,digital hydraulic pump/motor can replace conventional variable hydraulic pump/motor in many application fields.However,digital hydraulic components produce large hydraulic impact at variable moments,which will shorten the service life of mechanical components.Through the simulation analysis of the variable process of digital pump/motor,it is found that the discontinuous flow caused by displacement step changes is the fundamental cause of hydraulic impact.The data analysis results of experimental tests are in good agreement with the simulation analysis results.In view of hydraulic secondary components,a variable control method based on dual-mode operating characteristics is proposed.The TOPSIS algorithm is used to give comprehensive evaluation of the displacement control results after this method.The results show that the control quality of digital pump/motor after adopting the control method has been effectively improved,with an average improvement of about 40%.展开更多
A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm2, about 37% smalle...A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm2, about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DC-DC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18μm logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 ~tW, respectively, and the EEPROM size is 0.12 mm2.展开更多
基金Project(51405183)supported by the National Natural Science Foundation of China。
文摘Due to the advantages of low cost,fast response and pollution resistance,digital hydraulic pump/motor can replace conventional variable hydraulic pump/motor in many application fields.However,digital hydraulic components produce large hydraulic impact at variable moments,which will shorten the service life of mechanical components.Through the simulation analysis of the variable process of digital pump/motor,it is found that the discontinuous flow caused by displacement step changes is the fundamental cause of hydraulic impact.The data analysis results of experimental tests are in good agreement with the simulation analysis results.In view of hydraulic secondary components,a variable control method based on dual-mode operating characteristics is proposed.The TOPSIS algorithm is used to give comprehensive evaluation of the displacement control results after this method.The results show that the control quality of digital pump/motor after adopting the control method has been effectively improved,with an average improvement of about 40%.
基金Project(10039239) supported by the Industrial Strategic Technology Development Program Funded by the Ministry of Knowledge Economy, Korea
文摘A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm2, about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DC-DC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18μm logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 ~tW, respectively, and the EEPROM size is 0.12 mm2.
