On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising cloc...On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.展开更多
Significant high magnetic gradient field strength is essential to obtaining high-resolution images in a benchtop mag- netic resonance imaging （BT-MRI） system with permanent magnet. Extending minimum wire spacing and...Significant high magnetic gradient field strength is essential to obtaining high-resolution images in a benchtop mag- netic resonance imaging （BT-MRI） system with permanent magnet. Extending minimum wire spacing and maximum wire width of gradient coils is one of the key solutions to minimize the maximum current density so as to reduce the local heating and generate higher magnetic field gradient strength. However, maximum current density is hard to optimize together with field linearity, stored magnetic energy, and power dissipation by the traditional target field method. In this paper, a new multi-objective method is proposed to optimize the maximum current density, field linearity, stored magnetic energy, and power dissipation in MRI gradient coils. The simulation and experimental results show that the minimum wire spacings are improved by 159% and 62% for the transverse and longitudinal gradient coil respectively. The maximum wire width increases from 0.5 mm to 1.5 mm. Maximum gradient field strengths of 157 mT/m and 405 mT/m for transverse and lon- gitudinal coil are achieved, respectively. The experimental results in BT-MRI instrument demonstrate that the MRI images with in-plane resolution of 50 ~tm can be obtained by using the designed coils.展开更多
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415, 60971066, and 61006028)the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260)the National Key Lab Foundation,China (Grant No. ZHD200904)
文摘On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.
基金Project supported by the Natural Science Foundation of the Ministry of Science and Technology of China (Grant No.2011ZX05008004)the Science Fund of the Committee of Science and Technology of Beijing,China
文摘Significant high magnetic gradient field strength is essential to obtaining high-resolution images in a benchtop mag- netic resonance imaging （BT-MRI） system with permanent magnet. Extending minimum wire spacing and maximum wire width of gradient coils is one of the key solutions to minimize the maximum current density so as to reduce the local heating and generate higher magnetic field gradient strength. However, maximum current density is hard to optimize together with field linearity, stored magnetic energy, and power dissipation by the traditional target field method. In this paper, a new multi-objective method is proposed to optimize the maximum current density, field linearity, stored magnetic energy, and power dissipation in MRI gradient coils. The simulation and experimental results show that the minimum wire spacings are improved by 159% and 62% for the transverse and longitudinal gradient coil respectively. The maximum wire width increases from 0.5 mm to 1.5 mm. Maximum gradient field strengths of 157 mT/m and 405 mT/m for transverse and lon- gitudinal coil are achieved, respectively. The experimental results in BT-MRI instrument demonstrate that the MRI images with in-plane resolution of 50 ~tm can be obtained by using the designed coils.
