A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral com...A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.展开更多
目前数据中心规模迅速扩大和网络带宽大幅度提升,传统软件网络协议栈的处理器开销较大,并且难以满足众多数据中心应用程序在吞吐、延迟等方面的需求.远程直接内存访问(remote direct memory access,RDMA)技术采用零拷贝、内核旁路和处...目前数据中心规模迅速扩大和网络带宽大幅度提升,传统软件网络协议栈的处理器开销较大,并且难以满足众多数据中心应用程序在吞吐、延迟等方面的需求.远程直接内存访问(remote direct memory access,RDMA)技术采用零拷贝、内核旁路和处理器功能卸载等思想,能够高带宽、低延迟地读写远端主机内存数据.兼容以太网的RDMA技术正在数据中心领域展开应用,以太网RDMA网卡作为主要功能承载设备,对其部署发挥重要作用.综述从架构、优化和实现评估3个方面进行分析:1)对以太网RDMA网卡的通用架构进行了总结,并对其关键功能部件进行了介绍;2)重点阐述了存储资源、可靠传输和应用相关3方面的优化技术,包括面向网卡缓存资源的连接可扩展性和面向主机内存资源的注册访问优化,面向有损以太网实现可靠传输的拥塞控制、流量控制和重传机制优化,面向分布式存储中不同存储类型、数据库系统、云存储系统以及面向数据中心应用的多租户性能隔离、安全性、可编程性等方面的优化工作;3)调研了不同实现方式、评估方式.最后,给出总结和展望.展开更多
基金Projects(61203308,61309014)supported by the National Natural Science Foundation of China
文摘A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.
文摘目前数据中心规模迅速扩大和网络带宽大幅度提升,传统软件网络协议栈的处理器开销较大,并且难以满足众多数据中心应用程序在吞吐、延迟等方面的需求.远程直接内存访问(remote direct memory access,RDMA)技术采用零拷贝、内核旁路和处理器功能卸载等思想,能够高带宽、低延迟地读写远端主机内存数据.兼容以太网的RDMA技术正在数据中心领域展开应用,以太网RDMA网卡作为主要功能承载设备,对其部署发挥重要作用.综述从架构、优化和实现评估3个方面进行分析:1)对以太网RDMA网卡的通用架构进行了总结,并对其关键功能部件进行了介绍;2)重点阐述了存储资源、可靠传输和应用相关3方面的优化技术,包括面向网卡缓存资源的连接可扩展性和面向主机内存资源的注册访问优化,面向有损以太网实现可靠传输的拥塞控制、流量控制和重传机制优化,面向分布式存储中不同存储类型、数据库系统、云存储系统以及面向数据中心应用的多租户性能隔离、安全性、可编程性等方面的优化工作;3)调研了不同实现方式、评估方式.最后,给出总结和展望.
