The effect of substrate doping on the flatband and threshold voltages of a strained-Si/SiGe p metal-oxide semiconductor field-effect transistor（pMOSFET） has been studied.By physically deriving the models of the flat...The effect of substrate doping on the flatband and threshold voltages of a strained-Si/SiGe p metal-oxide semiconductor field-effect transistor（pMOSFET） has been studied.By physically deriving the models of the flatband and threshold voltages,which have been validated by numerical simulation and experimental data,the shift in the plateau from the inversion region to the accumulation region as the substrate doping increases has been explained.The proposed model can provide a valuable reference to the designers of strained-Si devices and has been implemented in software for extracting the parameters of a strained-Si MOSFET.展开更多
An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented...An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.展开更多
Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1-xGex/relaxd Si1-yGey（s-Si/s-SiGe/Si1-yGey） metal-oxide-semiconductor field-effect transistor ...Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1-xGex/relaxd Si1-yGey（s-Si/s-SiGe/Si1-yGey） metal-oxide-semiconductor field-effect transistor （PMOSFET）, analytical expressions of the threshold voltages for buried channel and surface channel are presented. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel （compressive strained SiGe） than in the surface channel （tensile strained Si）, because the hole mobility in the buried channel is higher than that in the surface channel. Thus they offer a good accuracy as compared with the results of device simulator ISE. With this model, the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted, such as Ge fraction, layer thickness, and doping concentration. This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si1-yGey metal-oxide-semiconductor field-effect transistor （MOSFET） designs.展开更多
The threshold voltage(V_(th))of the p-channel metal-oxide-semiconductor field-effect transistors(MOSFETs)is investigated via Silvaco-Atlas simulations.The main factors which influence the threshold voltage of p-channe...The threshold voltage(V_(th))of the p-channel metal-oxide-semiconductor field-effect transistors(MOSFETs)is investigated via Silvaco-Atlas simulations.The main factors which influence the threshold voltage of p-channel GaN MOSFETs are barrier heightΦ_(1,p),polarization charge density σ_(b),and equivalent unite capacitance C_(oc).It is found that the thinner thickness of p-GaN layer and oxide layer will acquire the more negative threshold voltage V_(th),and threshold voltage|V_(th)|increases with the reduction in p-GaN doping concentration and the work-function of gate metal.Meanwhile,the increase in gate dielectric relative permittivity may cause the increase in threshold voltage|V_(th)|.Additionally,the parameter influencing output current most is the p-GaN doping concentration,and the maximum current density is 9.5 mA/mm with p-type doping concentration of 9.5×10^(16) cm^(-3) at VGS=-12 V and VDS=-10 V.展开更多
In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering...In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.展开更多
In this paper, a threshold voltage model for high-k gate-dielectric metal-oxide-semiconductor field-effect transistors （MOSFETs） is developed, with more accurate boundary conditions of the gate dielectric derived th...In this paper, a threshold voltage model for high-k gate-dielectric metal-oxide-semiconductor field-effect transistors （MOSFETs） is developed, with more accurate boundary conditions of the gate dielectric derived through a conformal mapping transformation method to consider the fringing-field effects including the influences of high-k gate-dielectric and sidewall spacer. Comparing with similar models, the proposed model can be applied to general situations where the gate dielectric and sidewall spacer can have different dielectric constants. The influences of sidewall spacer and high-k gate dielectric on fringing field distribution of the gate dielectric and thus threshold voltage behaviours of a MOSFET are discussed in detail.展开更多
In this work, AlGaN/GaN FinFETs with different fin widths have been successfully fabricated, and the recessed-gate FinFETs are fabricated for comparison. The recessed-gate FinFETs exhibit higher transconductance value...In this work, AlGaN/GaN FinFETs with different fin widths have been successfully fabricated, and the recessed-gate FinFETs are fabricated for comparison. The recessed-gate FinFETs exhibit higher transconductance value and positive shift of threshold voltage. Moreover, with the fin width of the recessed-gate FinFETs increasing, the variations of both threshold voltage and the transconductance increase. Next, transfer characteristics of the recessed-gate FinFETs with different fin widths and recessed-gate depths are simulated by Silvaco software. The relationship between the threshold voltage and the AlGaN layer thickness has been investigated. The simulation results indicate that the slope of threshold voltage variation reduces with the fin width decreasing. Finally, a simplified threshold voltage model for recessed-gate FinFET is established,which agrees with both the experimental results and simulation results.展开更多
The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface...The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.展开更多
An Ni/Au Schottky contact on an AlGaN/GaN heterostructure has been prepared. By using the peak-conductance model, the threshold voltage and the series resistance of the AlGaN/GaN diode are simultaneously extracted fro...An Ni/Au Schottky contact on an AlGaN/GaN heterostructure has been prepared. By using the peak-conductance model, the threshold voltage and the series resistance of the AlGaN/GaN diode are simultaneously extracted from the conductance-voltage （G-V） curve and found to be in good agreement with the ones obtained by using the capacitance-voltage （C-V） curve integration and the plot of dV/d（ln I） versus current I. Thus, a method of directly and simultaneously extracting both the threshold voltage and the series resistance from the conductance-voltage curve for the AlGaN/GaN Schottky diode is developed.展开更多
Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models i...Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor（MOSFET） are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.展开更多
The total ionizing dose(TID) effect is a key cause for the degradation/failure of semiconductor device performance under energetic-particle irradiation. We developed a dynamic model of mobile particles and defects by ...The total ionizing dose(TID) effect is a key cause for the degradation/failure of semiconductor device performance under energetic-particle irradiation. We developed a dynamic model of mobile particles and defects by solving the rate equations and Poisson's equation simultaneously, to understand threshold voltage shifts induced by TID in silicon-based metal–oxide–semiconductor(MOS) devices. The calculated charged defect distribution and corresponding electric field under different TIDs are consistent with experiments. TID changes the electric field at the Si/SiO_(2) interface by inducing the accumulation of oxide charged defects nearby, thus shifting the threshold voltage accordingly. With increasing TID, the oxide charged defects increase to saturation, and the electric field increases following the universal 2/3 power law. Through analyzing the influence of TID on the interfacial electric field by different factors, we recommend that the radiation-hardened performance of devices can be improved by choosing a thin oxide layer with high permittivity and under high gate voltages.展开更多
In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along wit...In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.展开更多
We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overl...We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson＇s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.展开更多
Amorphous indium-gallium-zinc oxide(a-IGZO)thin films are prepared by pulsed laser deposition and fabricated into thin-film transistor(TFT)devices.In-situ x-ray photoelectron spectroscopy(XPS)illustrates that weakly b...Amorphous indium-gallium-zinc oxide(a-IGZO)thin films are prepared by pulsed laser deposition and fabricated into thin-film transistor(TFT)devices.In-situ x-ray photoelectron spectroscopy(XPS)illustrates that weakly bonded oxygen(O)atoms exist in a-IGZO thin films deposited at high O_(2) pressures,but these can be eliminated by vacuum annealing.The threshold voltage(V_(th))of the a-IGZO TFTs is shifted under positive gate bias,and the Vth shift is positively related to the deposition pressure.A temperature variation experiment in the range of 20 K-300 K demonstrates that an activation energy of 144 meV is required for the Vth shift,which is close to the activation energy required for the migration of weakly bonded O atoms in a-IGZO thin films.Accordingly,the Vth shift is attributed to the acceptor-like states induced by the accumulation of weakly bonded O atoms at the a-IGZO/SiO_(2) interface under positive gate bias.These results provide an insight into the mechanism responsible for the Vth shift of the a-IGZO TFTs and help in the production of reliable designs.展开更多
A grating surface can drive the liquid crystal molecules to orientate along the direction parallel or vertical to the projected plane of the grating surface. The nematic liquid crystal （NLC） cell manufactured with t...A grating surface can drive the liquid crystal molecules to orientate along the direction parallel or vertical to the projected plane of the grating surface. The nematic liquid crystal （NLC） cell manufactured with two pre-treated grating surface substrates may realize the vertical display, parallel display and twist display. In this paper, the threshold property of this NLC cell is investigated systematically. With the Frank elastic theory and the equivalent anchoring energy formula of grating surface substrate, the analytic expressions of the threshold voltage related to three displays are obtained, which are dependent on their geometrical parameters such as amplitude ~ and pitch A of the grating surface substrate. For a certain anchoring strength, the threshold voltage increases or decreases with the increase of the value δ/λ of the different displays.展开更多
The uniformity of threshold voltage and threshold current in the In2 Se3 nanowire-based phase change memory （PCM） devices is investigated. Based on the trap-limited transport model, amorphous layer thickness, trap d...The uniformity of threshold voltage and threshold current in the In2 Se3 nanowire-based phase change memory （PCM） devices is investigated. Based on the trap-limited transport model, amorphous layer thickness, trap density, and trap depth are considered to clarify their influences upon the threshold voltage and threshold current through simulations.展开更多
The hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide under the low gate voltage （LGV） （at Vg = Vth, where Yth is the threshold voltage） stress...The hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide under the low gate voltage （LGV） （at Vg = Vth, where Yth is the threshold voltage） stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV （Vg = Vth） stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage （GIDL） current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90 nm gate length LDD-NMOSFET with 1.4 nm gate oxide under the LGV stress at Yg = Yth with various drain biases. Experimental results show that the degradation slopes （n） range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET （0.5 - 0.6） and also that of the long gate length LDD MOSFET （- 0.8）.展开更多
A comparative investigation of the resistance and ability to trigger high voltage（HV） discharge for a single filament（SF） and multiple filaments（MFs） has been carried out.The experimental results show that the t...A comparative investigation of the resistance and ability to trigger high voltage（HV） discharge for a single filament（SF） and multiple filaments（MFs） has been carried out.The experimental results show that the trend of the breakdown threshold of the SF exactly follows that of its resistance,but this is not the case for the MF.The MF＇s resistance is much smaller than the SF＇s.However,the MF shows a slightly higher HV breakdown threshold than the SF.The underlying physics is that the measured resistance of the MF is collectively contributed by every filament in the MF while the HV breakdown threshold is determined by only one single discharging path.展开更多
The magnetoresistive random access memory process makes a great contribution to threshold voltage deterioration of metal-oxide-silicon field-effect transistors,especially on p-type devices.Herein,a method was proposed...The magnetoresistive random access memory process makes a great contribution to threshold voltage deterioration of metal-oxide-silicon field-effect transistors,especially on p-type devices.Herein,a method was proposed to reduce the threshold voltage degradation by utilizing back-side stress.Through the deposition of tensile material on the back side,positive charges generated by silicon-hydrogen bond breakage were inhibited,resulting in a potential reduction in threshold voltage shift by up to 20%.In addition,it was found that the method could only relieve silicon-hydrogen bond breakage physically,thus failing to provide a complete cure.However,it holds significant potential for applications where additional thermal budget is undesired.Furthermore,it was also concluded that the method used in this work is irreversible,with its effect sustained to the chip package phase,and it ensures competitive reliability of the resulting magnetic tunnel junction devices.展开更多
In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the...In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional （2D） potential model is proposed for the subthreshold region of junctionless SO1 FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.展开更多
基金Project supported by the Funds from the National Ministries and Commissions (Grant Nos. 51308040203 and 6139801)the Fundamental Research Funds for the Central Universities (Grant Nos. 72105499 and 72104089)the Natural Science Basic Research Plan in Shaanxi Province of China (Grant No. 2010JQ8008)
文摘The effect of substrate doping on the flatband and threshold voltages of a strained-Si/SiGe p metal-oxide semiconductor field-effect transistor（pMOSFET） has been studied.By physically deriving the models of the flatband and threshold voltages,which have been validated by numerical simulation and experimental data,the shift in the plateau from the inversion region to the accumulation region as the substrate doping increases has been explained.The proposed model can provide a valuable reference to the designers of strained-Si devices and has been implemented in software for extracting the parameters of a strained-Si MOSFET.
文摘An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.
基金Project supported by the National Defence Pre-research Foundation of China (Grant Nos. 51308040203,9140A08060407DZ0103,and 6139801)
文摘Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1-xGex/relaxd Si1-yGey（s-Si/s-SiGe/Si1-yGey） metal-oxide-semiconductor field-effect transistor （PMOSFET）, analytical expressions of the threshold voltages for buried channel and surface channel are presented. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel （compressive strained SiGe） than in the surface channel （tensile strained Si）, because the hole mobility in the buried channel is higher than that in the surface channel. Thus they offer a good accuracy as compared with the results of device simulator ISE. With this model, the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted, such as Ge fraction, layer thickness, and doping concentration. This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si1-yGey metal-oxide-semiconductor field-effect transistor （MOSFET） designs.
基金Project supported by the Key-Area Research and Development Program of Guangdong Province,China(Grant Nos.2020B010174001 and 2020B010171002)the Ningbo Science and Technology Innovation Program 2025(Grant No.2019B10123)the National Natural Science Foundation of China(Grant No.62074122).
文摘The threshold voltage(V_(th))of the p-channel metal-oxide-semiconductor field-effect transistors(MOSFETs)is investigated via Silvaco-Atlas simulations.The main factors which influence the threshold voltage of p-channel GaN MOSFETs are barrier heightΦ_(1,p),polarization charge density σ_(b),and equivalent unite capacitance C_(oc).It is found that the thinner thickness of p-GaN layer and oxide layer will acquire the more negative threshold voltage V_(th),and threshold voltage|V_(th)|increases with the reduction in p-GaN doping concentration and the work-function of gate metal.Meanwhile,the increase in gate dielectric relative permittivity may cause the increase in threshold voltage|V_(th)|.Additionally,the parameter influencing output current most is the p-GaN doping concentration,and the maximum current density is 9.5 mA/mm with p-type doping concentration of 9.5×10^(16) cm^(-3) at VGS=-12 V and VDS=-10 V.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60936005 and 61076097)the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China (Grant No. 708083)the Fundamental Research Funds for the Central Universities (Grant No. 20110203110012)
文摘In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.
基金Project supported by the National Natural Science Foundation of China （Grant No 60376019）.
文摘In this paper, a threshold voltage model for high-k gate-dielectric metal-oxide-semiconductor field-effect transistors （MOSFETs） is developed, with more accurate boundary conditions of the gate dielectric derived through a conformal mapping transformation method to consider the fringing-field effects including the influences of high-k gate-dielectric and sidewall spacer. Comparing with similar models, the proposed model can be applied to general situations where the gate dielectric and sidewall spacer can have different dielectric constants. The influences of sidewall spacer and high-k gate dielectric on fringing field distribution of the gate dielectric and thus threshold voltage behaviours of a MOSFET are discussed in detail.
基金Project supported by the National Key Research and Development Program of China(Grant No.2016YFB0400 300)the National Natural Science Foundation of China(Grant Nos.61574110,61574112,and 61474091)
文摘In this work, AlGaN/GaN FinFETs with different fin widths have been successfully fabricated, and the recessed-gate FinFETs are fabricated for comparison. The recessed-gate FinFETs exhibit higher transconductance value and positive shift of threshold voltage. Moreover, with the fin width of the recessed-gate FinFETs increasing, the variations of both threshold voltage and the transconductance increase. Next, transfer characteristics of the recessed-gate FinFETs with different fin widths and recessed-gate depths are simulated by Silvaco software. The relationship between the threshold voltage and the AlGaN layer thickness has been investigated. The simulation results indicate that the slope of threshold voltage variation reduces with the fin width decreasing. Finally, a simplified threshold voltage model for recessed-gate FinFET is established,which agrees with both the experimental results and simulation results.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61376099,11235008,and 61205003)
文摘The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.
基金the National Natural Science Foundation of China(Grant Nos.60890192,60876009,and 11174182)the Foundation of Key Laboratory,China
文摘An Ni/Au Schottky contact on an AlGaN/GaN heterostructure has been prepared. By using the peak-conductance model, the threshold voltage and the series resistance of the AlGaN/GaN diode are simultaneously extracted from the conductance-voltage （G-V） curve and found to be in good agreement with the ones obtained by using the capacitance-voltage （C-V） curve integration and the plot of dV/d（ln I） versus current I. Thus, a method of directly and simultaneously extracting both the threshold voltage and the series resistance from the conductance-voltage curve for the AlGaN/GaN Schottky diode is developed.
基金supported by the National Natural Science Foundation of China(Grant No.61274112)
文摘Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor（MOSFET） are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.
基金Project supported by the Science Challenge Project of China (Grant No.TZ2018004)the National Natural Science Foundation of China (Grant Nos.11975018 and 11775254)+1 种基金the National MCF Energy R&D Program of China (Grant No.2018YEF0308100)the outstanding member of Youth Innovation Promotion Association CAS (Grant No.Y202087)。
文摘The total ionizing dose(TID) effect is a key cause for the degradation/failure of semiconductor device performance under energetic-particle irradiation. We developed a dynamic model of mobile particles and defects by solving the rate equations and Poisson's equation simultaneously, to understand threshold voltage shifts induced by TID in silicon-based metal–oxide–semiconductor(MOS) devices. The calculated charged defect distribution and corresponding electric field under different TIDs are consistent with experiments. TID changes the electric field at the Si/SiO_(2) interface by inducing the accumulation of oxide charged defects nearby, thus shifting the threshold voltage accordingly. With increasing TID, the oxide charged defects increase to saturation, and the electric field increases following the universal 2/3 power law. Through analyzing the influence of TID on the interfacial electric field by different factors, we recommend that the radiation-hardened performance of devices can be improved by choosing a thin oxide layer with high permittivity and under high gate voltages.
文摘In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60936005 and 61076097)the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China(Grant No.708083)the Fundamental Research Funds for the Central Universities of China(Grant No.20110203110012)
文摘We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson＇s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.51771144 and 62104189)the Natural Science Foundation of Shaanxi Province,China(Grant Nos.2021JC-06,2019TD-020,and 2019JLM-30)+1 种基金the China Postdoctoral Science Foundation(Grant No.2020M683483)the Fundamental scientific research business expenses of Xi'an Jiaotong University(Grant No.XZY022020017).
文摘Amorphous indium-gallium-zinc oxide(a-IGZO)thin films are prepared by pulsed laser deposition and fabricated into thin-film transistor(TFT)devices.In-situ x-ray photoelectron spectroscopy(XPS)illustrates that weakly bonded oxygen(O)atoms exist in a-IGZO thin films deposited at high O_(2) pressures,but these can be eliminated by vacuum annealing.The threshold voltage(V_(th))of the a-IGZO TFTs is shifted under positive gate bias,and the Vth shift is positively related to the deposition pressure.A temperature variation experiment in the range of 20 K-300 K demonstrates that an activation energy of 144 meV is required for the Vth shift,which is close to the activation energy required for the migration of weakly bonded O atoms in a-IGZO thin films.Accordingly,the Vth shift is attributed to the acceptor-like states induced by the accumulation of weakly bonded O atoms at the a-IGZO/SiO_(2) interface under positive gate bias.These results provide an insight into the mechanism responsible for the Vth shift of the a-IGZO TFTs and help in the production of reliable designs.
基金Project supported by the Key Subject Construction Project of Hebei Province University of Chinathe National Natural Science Foundation of China (Grant Nos 10704022 and 60736042)
文摘A grating surface can drive the liquid crystal molecules to orientate along the direction parallel or vertical to the projected plane of the grating surface. The nematic liquid crystal （NLC） cell manufactured with two pre-treated grating surface substrates may realize the vertical display, parallel display and twist display. In this paper, the threshold property of this NLC cell is investigated systematically. With the Frank elastic theory and the equivalent anchoring energy formula of grating surface substrate, the analytic expressions of the threshold voltage related to three displays are obtained, which are dependent on their geometrical parameters such as amplitude ~ and pitch A of the grating surface substrate. For a certain anchoring strength, the threshold voltage increases or decreases with the increase of the value δ/λ of the different displays.
基金supported by the National Basic Research Program of China(Grant No.2011CBA00604)
文摘The uniformity of threshold voltage and threshold current in the In2 Se3 nanowire-based phase change memory （PCM） devices is investigated. Based on the trap-limited transport model, amorphous layer thickness, trap density, and trap depth are considered to clarify their influences upon the threshold voltage and threshold current through simulations.
基金Project supported by the National High Technology Research and Development Program of China （Grant No 2003AA1Z1630） and the National Natural Science Foundation of China （Grant No 60376024）.
文摘The hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide under the low gate voltage （LGV） （at Vg = Vth, where Yth is the threshold voltage） stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV （Vg = Vth） stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage （GIDL） current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90 nm gate length LDD-NMOSFET with 1.4 nm gate oxide under the LGV stress at Yg = Yth with various drain biases. Experimental results show that the degradation slopes （n） range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET （0.5 - 0.6） and also that of the long gate length LDD MOSFET （- 0.8）.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 11074027,60978014,61178022,11274053,and 11211120156)the Funds from Sci. & Tech. Deparment of Jilin Province,China (Grant No. 20111812)
文摘A comparative investigation of the resistance and ability to trigger high voltage（HV） discharge for a single filament（SF） and multiple filaments（MFs） has been carried out.The experimental results show that the trend of the breakdown threshold of the SF exactly follows that of its resistance,but this is not the case for the MF.The MF＇s resistance is much smaller than the SF＇s.However,the MF shows a slightly higher HV breakdown threshold than the SF.The underlying physics is that the measured resistance of the MF is collectively contributed by every filament in the MF while the HV breakdown threshold is determined by only one single discharging path.
基金Project supported by the National Natural Science Foundation of China(Grant No.51672246)the National Key Research and Development Program of China(Grant Nos.2017YFA0304302 and 2020AAA0109003)the Key Research and Development Program of Zhejiang Province,China(Grant No.2021C01002)。
文摘The magnetoresistive random access memory process makes a great contribution to threshold voltage deterioration of metal-oxide-silicon field-effect transistors,especially on p-type devices.Herein,a method was proposed to reduce the threshold voltage degradation by utilizing back-side stress.Through the deposition of tensile material on the back side,positive charges generated by silicon-hydrogen bond breakage were inhibited,resulting in a potential reduction in threshold voltage shift by up to 20%.In addition,it was found that the method could only relieve silicon-hydrogen bond breakage physically,thus failing to provide a complete cure.However,it holds significant potential for applications where additional thermal budget is undesired.Furthermore,it was also concluded that the method used in this work is irreversible,with its effect sustained to the chip package phase,and it ensures competitive reliability of the resulting magnetic tunnel junction devices.
基金supported by the Research Program of the National University of Defense Technology(Grant No.JC 13-06-04)
文摘In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional （2D） potential model is proposed for the subthreshold region of junctionless SO1 FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.
