The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms...The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms a graph to represent the static data-flow for the target circuit. A fault-model is defined at RT-Level. The ATPG method is then presented. Experimental results show that the ATPG method is time effective and can generate tests with fairly good quality, the fault coverage of some circuits is to be enhanced though.展开更多
基金supported by National Natural Science Foundation of China under grant No.69733010.
文摘The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms a graph to represent the static data-flow for the target circuit. A fault-model is defined at RT-Level. The ATPG method is then presented. Experimental results show that the ATPG method is time effective and can generate tests with fairly good quality, the fault coverage of some circuits is to be enhanced though.
