The synchronous tracking control problem of a hydraulic parallel manipulator with six degrees of freedom (DOF) is complicated since the inclusion of hydraulic elements increases the order of the system.To solve this p...The synchronous tracking control problem of a hydraulic parallel manipulator with six degrees of freedom (DOF) is complicated since the inclusion of hydraulic elements increases the order of the system.To solve this problem,cascade control method with an inner/outer-loop control structure is used,which masks the hydraulic dynamics with the inner-loop so that the designed controller takes into account of both the mechanical dynamics and the hydraulic dynamics of the manipulator.Furthermore,a cross-coupling control approach is introduced to the synchronous tracking control of the manipulator.The position synchronization error is developed by considering motion synchronization between each actuator joint and its adjacent ones based on the synchronous goal.Then,with the feedback of both position error and synchronization error,the tracking is proven to guarantee that both the position errors and synchronization errors asymptotically converge to zero.Moreover,the effectiveness of the proposed approach is verified by the experimental results performed with a 6-DOF hydraulic parallel manipulator.展开更多
We propose a single-poly MTP （multi-time programmable） cell consisting of one capacitor and two transistors based on MagnaChip＇s BCD process. The area of a unit cell is 37.743 75μm^2. The proposed single-poly MTP ...We propose a single-poly MTP （multi-time programmable） cell consisting of one capacitor and two transistors based on MagnaChip＇s BCD process. The area of a unit cell is 37.743 75μm^2. The proposed single-poly MTP cell is erased and programmed by the FN tunnelling scheme. We design a 256 bit MTP memory for PMICs （power management ICs） using the proposed single-poly MTP cells. For small-area designs, we propose a selection circuit between V10V and VSV, and a WL （word-line） driver by simplifying its logic circuit. We reduce the total layout area by using pumped internal node voltages from a seven-stage cross-coupled charge pump for V10V （=10 V） and V5V （=5 V） without any additional charge pumps. The layout size of the designed 256 bit MTP memory is 618.250 μm × 437.425μm.展开更多
基金Project(50375139) supported by the National Natural Science Foundation of ChinaProject(NCET-04-0545) supported by the New Century Excellent Talent Plan of the Ministry of Education of China
文摘The synchronous tracking control problem of a hydraulic parallel manipulator with six degrees of freedom (DOF) is complicated since the inclusion of hydraulic elements increases the order of the system.To solve this problem,cascade control method with an inner/outer-loop control structure is used,which masks the hydraulic dynamics with the inner-loop so that the designed controller takes into account of both the mechanical dynamics and the hydraulic dynamics of the manipulator.Furthermore,a cross-coupling control approach is introduced to the synchronous tracking control of the manipulator.The position synchronization error is developed by considering motion synchronization between each actuator joint and its adjacent ones based on the synchronous goal.Then,with the feedback of both position error and synchronization error,the tracking is proven to guarantee that both the position errors and synchronization errors asymptotically converge to zero.Moreover,the effectiveness of the proposed approach is verified by the experimental results performed with a 6-DOF hydraulic parallel manipulator.
基金Project supported by the Second Stage of Brain Korea 21 Projectssupported by Industrial Strategic Technology Development Program funded by the Ministry of Knowledge Economy (MKE,Korea)(10039239,"Development of Power Management System SoC Supporting Multi-Battery-Cells and Multi-Energy-Sources for Smart Phones and Smart Devices")
文摘We propose a single-poly MTP （multi-time programmable） cell consisting of one capacitor and two transistors based on MagnaChip＇s BCD process. The area of a unit cell is 37.743 75μm^2. The proposed single-poly MTP cell is erased and programmed by the FN tunnelling scheme. We design a 256 bit MTP memory for PMICs （power management ICs） using the proposed single-poly MTP cells. For small-area designs, we propose a selection circuit between V10V and VSV, and a WL （word-line） driver by simplifying its logic circuit. We reduce the total layout area by using pumped internal node voltages from a seven-stage cross-coupled charge pump for V10V （=10 V） and V5V （=5 V） without any additional charge pumps. The layout size of the designed 256 bit MTP memory is 618.250 μm × 437.425μm.
