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Design of quaternary logic circuits based on source-coupled logic
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作者 吴海霞 屈晓楠 +2 位作者 蔡起龙 夏乾斌 仲顺安 《Journal of Beijing Institute of Technology》 EI CAS 2013年第1期49-54,共6页
In order to improve the performance of arithmetic very large-scale integration (VLSI) sys- tem, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode (MVCM) by using dynamic... In order to improve the performance of arithmetic very large-scale integration (VLSI) sys- tem, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode (MVCM) by using dynamic source-coupled logic (SCL). Its key components, the comparator and the output generator are both based on differential-pair circuit (DPC), and the latter is constructed by using the structure of DPC trees. The pre-charge evaluates logic style makes a steady current flow cut off, thereby greatly saving the power dissipation. The combination of multiple-valued source- coupled logic and differential-pair circuit makes it lower power consumption and more compact. The performance is evaluated by HSPICE simulation with 0.18 ~m CMOS technology. The power dissipa- tion, transistor numbers and delay are superior to corresponding binary CMOS implementation. Mul- tiple-valued logic will be the potential solution for the high performance arithmetic VLSI system in the future. 展开更多
关键词 multiple-valued logic multiple-valued current mode source-coupled logic scl cir-cuit
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