A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacr...A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.展开更多
基于GaAs赝高电子迁移率晶体管（PHEMT）工艺,研制了一种5-12 GHz的收发一体多功能芯片（T/R MFC）,其具有噪声低、增益高和中等功率等特点。电路由低噪声放大器和多个单刀双掷（SPDT）开关构成。为了获得较低的噪声系数和较大的增益,...基于GaAs赝高电子迁移率晶体管（PHEMT）工艺,研制了一种5-12 GHz的收发一体多功能芯片（T/R MFC）,其具有噪声低、增益高和中等功率等特点。电路由低噪声放大器和多个单刀双掷（SPDT）开关构成。为了获得较低的噪声系数和较大的增益,低噪声放大器采用自偏置三级级联拓扑结构;为了获得较高的隔离度和较低的插入损耗,SPDT开关采用串并联结构。测试结果表明,在5-12 GHz频段内,收发一体多功能芯片的小信号增益大于26 d B,噪声系数小于4 d B,输入/输出电压驻波比小于2.0,1 d B压缩点输出功率大于15 d Bm。其中,放大器为单电源5 V供电,静态电流小于120 m A;开关控制电压为-5 V/0 V。芯片尺寸为2.65 mm×2.0 mm。展开更多
基金Supported by the Fundamental Research Funds for the Central Universities(ZYGX2010J039)the Defense Pre-Research Foundation of China(9140A12020311DZ0202)the Program for NCET(NCET-12-0099)
文摘A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.
文摘基于GaAs赝高电子迁移率晶体管（PHEMT）工艺,研制了一种5-12 GHz的收发一体多功能芯片（T/R MFC）,其具有噪声低、增益高和中等功率等特点。电路由低噪声放大器和多个单刀双掷（SPDT）开关构成。为了获得较低的噪声系数和较大的增益,低噪声放大器采用自偏置三级级联拓扑结构;为了获得较高的隔离度和较低的插入损耗,SPDT开关采用串并联结构。测试结果表明,在5-12 GHz频段内,收发一体多功能芯片的小信号增益大于26 d B,噪声系数小于4 d B,输入/输出电压驻波比小于2.0,1 d B压缩点输出功率大于15 d Bm。其中,放大器为单电源5 V供电,静态电流小于120 m A;开关控制电压为-5 V/0 V。芯片尺寸为2.65 mm×2.0 mm。
