The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the tradi...The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper, a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation （CSMC） 0.5 μm complementary metal-oxide-semiconductor transistor （CMOS） technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit （ROIC） with a larger array, such as 320×240 size array.展开更多
The output of uncooled microbolometer is nonuniform, and the traditional two-point nonuniformity correction method requires a tight restriction on substrate temperature. The circuit proposed by this article can relax ...The output of uncooled microbolometer is nonuniform, and the traditional two-point nonuniformity correction method requires a tight restriction on substrate temperature. The circuit proposed by this article can relax the restriction on the substrate temperature and perform nonuniformity correction when reading out the image signal. The dummy pixels reduce static current. And the Column shared DACs transfer correction data to the gates of MOS transistors and the positive reference edge of amplifier, to control the bias current of detector and dummy one, and set the start point of integration. This circuit has higher sensitivity, wider dynamic range, and frame frequency of more than 30 Hz for 128×128 array. PSPICE simulation results seem that this circuit functions well.展开更多
Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end ...Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end circuit design.In this paper,we present a 0.18μm CMOS front-end readout circuit for low noise CdZnTe detectors in tens of pF capacitance.Solutions to the noise and gate leak problems in DSM technologies are discussed in detail.A prototype chip was designed,with a charge sensitive preamplifier,a 4th order semi-Gaussian shaper and several output drivers.Test results show that the chip has an equivalent noise charge of 164 e,without connecting it to a detector,with an integral nonlinearity of<0.21%and differential nonlinearity of<3.75%.展开更多
A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuo...A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuous-time semi-Gaussian filter is chosen to avoid switch noise.The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application.The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology.Test results show the functions of the readout integrated circuit are correct.The equivalent noise charge with no detector connected is 500–700 e in the typical mode,the gain is tunable within 13–130 mV/fC and the peaking time varies from 0.7 to 1.6 μs,in which the average gain is about 20.5 mV/fC,and the linearity reaches 99.2%.展开更多
线性雪崩光电二极管(Avalanche photodiode,APD)焦平面红外探测器有着广泛应用场景,APD探测器耦合具有多种模式的读出电路可在有限像元面积内实现多模式探测,提升探测系统集成度。本文设计了一种具有红外热成像模式、门控3D成像模式、...线性雪崩光电二极管(Avalanche photodiode,APD)焦平面红外探测器有着广泛应用场景,APD探测器耦合具有多种模式的读出电路可在有限像元面积内实现多模式探测,提升探测系统集成度。本文设计了一种具有红外热成像模式、门控3D成像模式、激光测距模式和异步激光脉冲探测模式的APD读出电路,四种模式复用输入级电路。通过Krummenacher结构抑制背景辐射影响,扩展了光子飞行时间探测范围;提出一种改进型时刻鉴别电路,通过减小时刻鉴别误差提升距离测量精度。读出电路采用0.18μm 3.3 V CMOS工艺设计,阵列规模128×128、像元中心距30μm,最大电荷容量3.74 Me^(-)。仿真结果表明,激光测距模式,在积分电容13 f F、背景电流1~150 nA条件下,背景电流响应幅值≤1.35 m V,远小于激光响应电流500 nA时280 m V的响应幅值;异步激光脉冲探测模式的幅值灵敏度约110 nA、脉宽灵敏度约4 ns;改进型时刻鉴别电路对于150~500 nA的激光脉冲响应,时刻鉴别误差约4 ns。本文设计的多模式复用APD读出电路具有一定工程应用价值。展开更多
基金supported by the Fundamental Research Funds for the Central Universities under Grant No. 2009JBM001
文摘The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper, a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation （CSMC） 0.5 μm complementary metal-oxide-semiconductor transistor （CMOS） technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit （ROIC） with a larger array, such as 320×240 size array.
基金the National Science Foundation of China (No:60377036).
文摘The output of uncooled microbolometer is nonuniform, and the traditional two-point nonuniformity correction method requires a tight restriction on substrate temperature. The circuit proposed by this article can relax the restriction on the substrate temperature and perform nonuniformity correction when reading out the image signal. The dummy pixels reduce static current. And the Column shared DACs transfer correction data to the gates of MOS transistors and the positive reference edge of amplifier, to control the bias current of detector and dummy one, and set the start point of integration. This circuit has higher sensitivity, wider dynamic range, and frame frequency of more than 30 Hz for 128×128 array. PSPICE simulation results seem that this circuit functions well.
基金supported by the National Natural Science Foundation of China (No.61006021)
文摘Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end circuit design.In this paper,we present a 0.18μm CMOS front-end readout circuit for low noise CdZnTe detectors in tens of pF capacitance.Solutions to the noise and gate leak problems in DSM technologies are discussed in detail.A prototype chip was designed,with a charge sensitive preamplifier,a 4th order semi-Gaussian shaper and several output drivers.Test results show that the chip has an equivalent noise charge of 164 e,without connecting it to a detector,with an integral nonlinearity of<0.21%and differential nonlinearity of<3.75%.
基金Supported by the National Natural Science Foundation of China (No.40704025)
文摘A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuous-time semi-Gaussian filter is chosen to avoid switch noise.The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application.The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology.Test results show the functions of the readout integrated circuit are correct.The equivalent noise charge with no detector connected is 500–700 e in the typical mode,the gain is tunable within 13–130 mV/fC and the peaking time varies from 0.7 to 1.6 μs,in which the average gain is about 20.5 mV/fC,and the linearity reaches 99.2%.
文摘线性雪崩光电二极管(Avalanche photodiode,APD)焦平面红外探测器有着广泛应用场景,APD探测器耦合具有多种模式的读出电路可在有限像元面积内实现多模式探测,提升探测系统集成度。本文设计了一种具有红外热成像模式、门控3D成像模式、激光测距模式和异步激光脉冲探测模式的APD读出电路,四种模式复用输入级电路。通过Krummenacher结构抑制背景辐射影响,扩展了光子飞行时间探测范围;提出一种改进型时刻鉴别电路,通过减小时刻鉴别误差提升距离测量精度。读出电路采用0.18μm 3.3 V CMOS工艺设计,阵列规模128×128、像元中心距30μm,最大电荷容量3.74 Me^(-)。仿真结果表明,激光测距模式,在积分电容13 f F、背景电流1~150 nA条件下,背景电流响应幅值≤1.35 m V,远小于激光响应电流500 nA时280 m V的响应幅值;异步激光脉冲探测模式的幅值灵敏度约110 nA、脉宽灵敏度约4 ns;改进型时刻鉴别电路对于150~500 nA的激光脉冲响应,时刻鉴别误差约4 ns。本文设计的多模式复用APD读出电路具有一定工程应用价值。
