A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability（PBTI） stress ...A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability（PBTI） stress based on the recovery measurement. In our case, the extracted energy distribution of negative charges shows an obvious dependence on energy,and the energy level of the largest energy density of negative charges is 0.01 eV above the conduction band of silicon. The charge energy distribution below that energy level shows strong dependence on the stress voltage.展开更多
Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nm...Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors （nMOSFETs） are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability （PBTI） and hot carrier injection （HCI） characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.展开更多
The positive bias temperature instability（PBTI） degradations of high-k/metal gate（HK/MG） n MOSFETs with thin TiN capping layers（1.4 nm and 2.4 nm） are systemically investigated. In this paper, the trap energy di...The positive bias temperature instability（PBTI） degradations of high-k/metal gate（HK/MG） n MOSFETs with thin TiN capping layers（1.4 nm and 2.4 nm） are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI（90℃,125℃, 160℃） are studied and activation energy（Ea） values（0.13 eV and 0.15 eV） are extracted. Although the equivalent oxide thickness（EOT） values of two TiN thickness values are almost similar（0.85 nm and 0.87 nm）, the 2.4-nm TiN one（thicker Ti N capping layer） shows better PBTI reliability（13.41% at 0.9 V, 90℃, 1000 s）. This is due to the better interfacial layer/high-k（IL/HK） interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.展开更多
Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. ...Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.展开更多
Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium-gallium-zinc oxide thin film transistor, which adopts an elevated-...Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium-gallium-zinc oxide thin film transistor, which adopts an elevated-metal metal-oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction. The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the back-channel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device （L=2 μm）. It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.展开更多
In a steady-state plasma,the loss rate of plasma particles to the chamber wall and surfaces in contact with plasma is balanced by the ionization rate of background neutrals in the hot-filament discharges.The balance b...In a steady-state plasma,the loss rate of plasma particles to the chamber wall and surfaces in contact with plasma is balanced by the ionization rate of background neutrals in the hot-filament discharges.The balance between the loss rate and ionization rate of plasma particles(electrons and ions)maintains quasi-neutrality of the bulk plasma.In the presence of an external perturbation,it tries to retain its quasi-neutrality condition.In this work,we studied how the properties of bulk plasma are affected by an external DC potential perturbation.An auxiliary biased metal disk electrode was used to introduce a potential perturbation to the plasma medium.A single Langmuir probe and an emissive probe,placed in the line of the discharge axis,were used for the characterization of the bulk plasma.It is observed that only positive bias to the auxiliary metal disk increases the plasma potential,electron temperature,and plasma density but these plasma parameters remain unaltered when the disk is biased with a negative potential with respect to plasma potential.The observed plasma parameters for two different-sized,positively as well as negatively biased,metal disks are compared and found inconsistent with the existing theoretical model at large positive bias voltages.The role of the primary energetic electrons population in determining the plasma parameters is discussed.The experimentally observed results are qualitatively explained on the basis of electrostatic confinement arising due to the loss of electrons to a biased metal disk electrode.展开更多
The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transisto...The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transistors. It is found that the time dependence of threshold voltage shift can be well described by a stretched exponential equation in which the time constant τ is found to be temperature dependent. Based on Arrhenius plots, an average effective energy barrier Eτ stress= 0.72 eV for the PBS process and an average effective energy barrier Eτ recovery= 0.58 eV for the recovery process are extracted respectively. A charge trapping/detrapping model is used to explain the threshold voltage shift in both the PBS and the recovery process. The influence of gate bias stress on transistor performance is one of the most critical issues for practical device development.展开更多
Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature （NBT-PBT-NBT） stress conditions are investigated in this paper. It is found that for all de...Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature （NBT-PBT-NBT） stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.展开更多
基金Project supported by the National Science&Technology Major Projects of the Ministry of Science and Technology of China(Grant No.2009ZX02035)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)
文摘A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability（PBTI） stress based on the recovery measurement. In our case, the extracted energy distribution of negative charges shows an obvious dependence on energy,and the energy level of the largest energy density of negative charges is 0.01 eV above the conduction band of silicon. The charge energy distribution below that energy level shows strong dependence on the stress voltage.
基金Supported by the National Program on Key Basic Research Project of China under Grant No 2011CBA00607the National Natural Science Foundation of China under Grant Nos 61106089 and 61376097the Zhejiang Provincial Natural Science Foundation of China under Grant No LR14F040001
文摘Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors （nMOSFETs） are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability （PBTI） and hot carrier injection （HCI） characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.
基金Project supported by the National High Technology Research and Development Program of China(Grant No.SS2015AA010601)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)
文摘The positive bias temperature instability（PBTI） degradations of high-k/metal gate（HK/MG） n MOSFETs with thin TiN capping layers（1.4 nm and 2.4 nm） are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI（90℃,125℃, 160℃） are studied and activation energy（Ea） values（0.13 eV and 0.15 eV） are extracted. Although the equivalent oxide thickness（EOT） values of two TiN thickness values are almost similar（0.85 nm and 0.87 nm）, the 2.4-nm TiN one（thicker Ti N capping layer） shows better PBTI reliability（13.41% at 0.9 V, 90℃, 1000 s）. This is due to the better interfacial layer/high-k（IL/HK） interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.
基金Supported by the National Science and Technology Major Project of China under Grant No 2011ZX02708-003the National Natural Science Foundation of China under Grant No 61504165the Opening Project of Key Laboratory of Microelectronics Devices and Integrated Technology of Institute of Microelectronics of Chinese Academy of Sciences
文摘Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.
基金Project supported by the Science and Technology Program of Suzhou City,China(Grant No.SYG201538)the National Natural Science Foundation of China(Grant No.61574096)
文摘Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium-gallium-zinc oxide thin film transistor, which adopts an elevated-metal metal-oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction. The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the back-channel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device （L=2 μm）. It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.
文摘In a steady-state plasma,the loss rate of plasma particles to the chamber wall and surfaces in contact with plasma is balanced by the ionization rate of background neutrals in the hot-filament discharges.The balance between the loss rate and ionization rate of plasma particles(electrons and ions)maintains quasi-neutrality of the bulk plasma.In the presence of an external perturbation,it tries to retain its quasi-neutrality condition.In this work,we studied how the properties of bulk plasma are affected by an external DC potential perturbation.An auxiliary biased metal disk electrode was used to introduce a potential perturbation to the plasma medium.A single Langmuir probe and an emissive probe,placed in the line of the discharge axis,were used for the characterization of the bulk plasma.It is observed that only positive bias to the auxiliary metal disk increases the plasma potential,electron temperature,and plasma density but these plasma parameters remain unaltered when the disk is biased with a negative potential with respect to plasma potential.The observed plasma parameters for two different-sized,positively as well as negatively biased,metal disks are compared and found inconsistent with the existing theoretical model at large positive bias voltages.The role of the primary energetic electrons population in determining the plasma parameters is discussed.The experimentally observed results are qualitatively explained on the basis of electrostatic confinement arising due to the loss of electrons to a biased metal disk electrode.
基金Project supported by the National Basic Research Program of China(Grant Nos.2011CB301900 and 2011CB922100)the Priority Academic Program Development of Jiangsu Higher Education Institutions,China
文摘The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transistors. It is found that the time dependence of threshold voltage shift can be well described by a stretched exponential equation in which the time constant τ is found to be temperature dependent. Based on Arrhenius plots, an average effective energy barrier Eτ stress= 0.72 eV for the PBS process and an average effective energy barrier Eτ recovery= 0.58 eV for the recovery process are extracted respectively. A charge trapping/detrapping model is used to explain the threshold voltage shift in both the PBS and the recovery process. The influence of gate bias stress on transistor performance is one of the most critical issues for practical device development.
基金Project supported by the National Natural Science Foundation of China （Grant No 60206006）, the Program for New Century Excellent Talents of Ministry of Education of China （Grant No 681231366）, the National Defense Pre-Research Foundation of China （Grant No 51308040103） and the Key Project of Chinese Ministry of Education （Grant No 104172）.
文摘Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature （NBT-PBT-NBT） stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.
