The Q-ary low-density parity-check（LDPC） coded high order partial response continuous phase modulation（PR-CPM） with double iterative loops is investigated. This scheme shows significant improvements in power and b...The Q-ary low-density parity-check（LDPC） coded high order partial response continuous phase modulation（PR-CPM） with double iterative loops is investigated. This scheme shows significant improvements in power and bandwidth efficiency, but at the expense of long iterative decoding delay and computational complexity induced by the improper match between the demodulator and the decoder. To address this issue, the convergence behavior of Q-ary LDPC coded CPM is investigated for the Q=2 and Q〉2 cases, and an optimized design method based on the extrinsic information transfer chart is proposed to improve the systematic iterative efficiency. Simulation results demonstrate that the proposed method can achieve a perfect tradeoff between iterative decoding delay and bit error rate performance to satisfy real-time applications.展开更多
基金supported by the National Natural Science Foundation of China(61403093)the Science Foundation of Heilongjiang Province of China for Returned Scholars(LC2013C22)the Assisted Project by Heilongjiang Province of China Postdoctoral Funds for Scientific Research Initiation(LBH-Q14048)
文摘The Q-ary low-density parity-check（LDPC） coded high order partial response continuous phase modulation（PR-CPM） with double iterative loops is investigated. This scheme shows significant improvements in power and bandwidth efficiency, but at the expense of long iterative decoding delay and computational complexity induced by the improper match between the demodulator and the decoder. To address this issue, the convergence behavior of Q-ary LDPC coded CPM is investigated for the Q=2 and Q〉2 cases, and an optimized design method based on the extrinsic information transfer chart is proposed to improve the systematic iterative efficiency. Simulation results demonstrate that the proposed method can achieve a perfect tradeoff between iterative decoding delay and bit error rate performance to satisfy real-time applications.
