A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge （ESD） protection circuits on the performance of radio...A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge （ESD） protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35μm 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.展开更多
The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor（Fin FET） device. Firstly, the structure of the dual-layer spa...The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor（Fin FET） device. Firstly, the structure of the dual-layer spacers and the gate parasitic capacitors are thoroughly analyzed. Then, the Cartesian coordinate is transferred into the elliptic coordinate and the equivalent fringe capacitance model can be built-up by some arithmetical operations. In order to validate our proposed model, the comparison of statistical analysis between the proposed calculation and the 3D-TCAD simulation has been carried out, and several different material combinations of the dual-k structure have been considered. The results show that the proposed analytical model can accurately calculate the fringe capacitance of the Fin FET device with dual-k spacers.展开更多
In this paper,ground-signal-ground type through-silicon vias（TSVs） exploiting air gaps as insulation layers are designed,analyzed and simulated for applications in millimeter wave.The compact wideband equivalent-cir...In this paper,ground-signal-ground type through-silicon vias（TSVs） exploiting air gaps as insulation layers are designed,analyzed and simulated for applications in millimeter wave.The compact wideband equivalent-circuit model and passive elements（RLGC） parameters based on the physical parameters are presented with the frequency up to 100 GHz.The parasitic capacitance of TSVs can be approximated as the dielectric capacitance of air gaps when the thickness of air gaps is greater than 0.75 μm.Therefore,the applied voltage of TSVs only needs to achieve the flatband voltage,and there is no need to indicate the threshold voltage.This is due to the small permittivity of air gaps.The proposed model shows good agreement with the simulation results of ADS and Ansoft＇s HFSS over a wide frequency range.展开更多
The T-gate stem height of In Al As/In Ga As In P-based high electron mobility transistor(HEMT) is increased from165 nm to 250 nm. The influences of increasing the gate stem height on the direct current(DC) and radio f...The T-gate stem height of In Al As/In Ga As In P-based high electron mobility transistor(HEMT) is increased from165 nm to 250 nm. The influences of increasing the gate stem height on the direct current(DC) and radio frequency(RF)performances of device are investigated. A 120-nm-long gate, 250-nm-high gate stem device exhibits a higher threshold voltage(Vth) of 60 m V than a 120-nm-long gate devices with a short gate stem, caused by more Pt distributions on the gate foot edges of the high Ti/Pt/Au gate. The Pt distribution in Schottky contact metal is found to increase with the gate stem height or the gate length increasing, and thus enhancing the Schottky barrier height and expanding the gate length,which can be due to the increased internal tensile stress of Pt. The more Pt distributions for the high gate stem device also lead to more obvious Pt sinking, which reduces the distance between the gate and the In Ga As channel so that the transconductance(gm) of the high gate stem device is 70 m S/mm larger than that of the short stem device. As for the RF performances,the gate extrinsic parasitic capacitance decreases and the intrinsic transconductance increases after the gate stem height has been increased, so the RF performances of device are obviously improved. The high gate stem device yields a maximum ft of 270 GHz and fmax of 460 GHz, while the short gate stem device has a maximum ft of 240 GHz and the fmax of 370 GHz.展开更多
文摘A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge （ESD） protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35μm 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61574056 and 61204038)the Natural Science Foundation of Shanghai,China(Grant No.14ZR1412000)
文摘The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor（Fin FET） device. Firstly, the structure of the dual-layer spacers and the gate parasitic capacitors are thoroughly analyzed. Then, the Cartesian coordinate is transferred into the elliptic coordinate and the equivalent fringe capacitance model can be built-up by some arithmetical operations. In order to validate our proposed model, the comparison of statistical analysis between the proposed calculation and the 3D-TCAD simulation has been carried out, and several different material combinations of the dual-k structure have been considered. The results show that the proposed analytical model can accurately calculate the fringe capacitance of the Fin FET device with dual-k spacers.
基金Project supported by the National Basic Research Program of China(Grant No.2014CB339900)the National Natural Science Foundation of China(Grant Nos.61376039,61334003,61574104,and 61474088)
文摘In this paper,ground-signal-ground type through-silicon vias（TSVs） exploiting air gaps as insulation layers are designed,analyzed and simulated for applications in millimeter wave.The compact wideband equivalent-circuit model and passive elements（RLGC） parameters based on the physical parameters are presented with the frequency up to 100 GHz.The parasitic capacitance of TSVs can be approximated as the dielectric capacitance of air gaps when the thickness of air gaps is greater than 0.75 μm.Therefore,the applied voltage of TSVs only needs to achieve the flatband voltage,and there is no need to indicate the threshold voltage.This is due to the small permittivity of air gaps.The proposed model shows good agreement with the simulation results of ADS and Ansoft＇s HFSS over a wide frequency range.
基金Project supported by the National Natural Science Foundation of China(Grant No.61434006)。
文摘The T-gate stem height of In Al As/In Ga As In P-based high electron mobility transistor(HEMT) is increased from165 nm to 250 nm. The influences of increasing the gate stem height on the direct current(DC) and radio frequency(RF)performances of device are investigated. A 120-nm-long gate, 250-nm-high gate stem device exhibits a higher threshold voltage(Vth) of 60 m V than a 120-nm-long gate devices with a short gate stem, caused by more Pt distributions on the gate foot edges of the high Ti/Pt/Au gate. The Pt distribution in Schottky contact metal is found to increase with the gate stem height or the gate length increasing, and thus enhancing the Schottky barrier height and expanding the gate length,which can be due to the increased internal tensile stress of Pt. The more Pt distributions for the high gate stem device also lead to more obvious Pt sinking, which reduces the distance between the gate and the In Ga As channel so that the transconductance(gm) of the high gate stem device is 70 m S/mm larger than that of the short stem device. As for the RF performances,the gate extrinsic parasitic capacitance decreases and the intrinsic transconductance increases after the gate stem height has been increased, so the RF performances of device are obviously improved. The high gate stem device yields a maximum ft of 270 GHz and fmax of 460 GHz, while the short gate stem device has a maximum ft of 240 GHz and the fmax of 370 GHz.
