In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC...In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.展开更多
A novel architecture for computing the fast Fourier transform ( FFT ) on programmable devices is presented.To improve the system operation speed , a hybrid parallel FFT algorithm is used.Results indicate that the use ...A novel architecture for computing the fast Fourier transform ( FFT ) on programmable devices is presented.To improve the system operation speed , a hybrid parallel FFT algorithm is used.Results indicate that the use of an 8×8parallel structure for realizing the 64-point FFT leads to a 8times higher processing speed compared with its counterparts employing other series of techniques.展开更多
Semiconductor quantum dot structure provides a promising basis for quantum information processing, within which to reveal the quantum phase and charge transport is one of the most important issues. In this paper, by m...Semiconductor quantum dot structure provides a promising basis for quantum information processing, within which to reveal the quantum phase and charge transport is one of the most important issues. In this paper, by means of the numerical renormalization group technique, we study the quantum phase transition and the charge transport for a parallel triple dot device in the strongly correlated limit, focusing on the effect of inter-dot hopping t beyond the Kondo regime. We find the quantum behaviors depend closely on the initial electron number on the dots, and the present model may map to single,double, and side-coupled impurity models in different parameter spaces. An orbital spin-1/2 Kondo effect between the conduction leads and the bonding orbital, and several magnetic-frustration phases are demonstrated when t is adjusted to different regimes. To understand these phenomena, a canonical transformation of the energy levels is given, and important physical quantities with respect to increasing t and necessary theoretical discussions are shown.展开更多
文摘In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.
基金Supported by the National Natural Science Foundation of China(60801052)the Aeronautical Science Foundation of China(2009ZC52036)+1 种基金the Ph.D.Programs Foundation of China's Ministry of Education(200802871056)the Nanjing University of Aeronautics & Astronautics Research Funding(NS2010109,NS2010114)
文摘A novel architecture for computing the fast Fourier transform ( FFT ) on programmable devices is presented.To improve the system operation speed , a hybrid parallel FFT algorithm is used.Results indicate that the use of an 8×8parallel structure for realizing the 64-point FFT leads to a 8times higher processing speed compared with its counterparts employing other series of techniques.
基金Project supported by the National Natural Science Foundation of China(Grant No.11504102)the Scientific Research Items Foundation of Hubei Educational Committee(Grant Nos.Q20161803 and D20171803)the Doctoral Scientific Research Foundation of Hubei University of Automotive Technology(Grant No.BK201407)
文摘Semiconductor quantum dot structure provides a promising basis for quantum information processing, within which to reveal the quantum phase and charge transport is one of the most important issues. In this paper, by means of the numerical renormalization group technique, we study the quantum phase transition and the charge transport for a parallel triple dot device in the strongly correlated limit, focusing on the effect of inter-dot hopping t beyond the Kondo regime. We find the quantum behaviors depend closely on the initial electron number on the dots, and the present model may map to single,double, and side-coupled impurity models in different parameter spaces. An orbital spin-1/2 Kondo effect between the conduction leads and the bonding orbital, and several magnetic-frustration phases are demonstrated when t is adjusted to different regimes. To understand these phenomena, a canonical transformation of the energy levels is given, and important physical quantities with respect to increasing t and necessary theoretical discussions are shown.
