ADSP-TS101 is a high performance DSP with good properties of parallel processing and high speed.According to the real-time processing requirements of underwater acoustic communication algorithms,a real-time parallel p...ADSP-TS101 is a high performance DSP with good properties of parallel processing and high speed.According to the real-time processing requirements of underwater acoustic communication algorithms,a real-time parallel processing system with multi-channel synchronous sample,which is composed of multiple ADSP-TS101s,is designed and carried out.For the hardware design,field programmable gate array(FPGA)logical control is adopted for the design of multi-channel synchronous sample module and cluster/data flow associated pin connection mode is adopted for multiprocessing parallel processing configuration respectively.And the software is optimized by two kinds of communication ways:broadcast writing way through shared bus and point-to-point way through link ports.Through the whole system installation,connective debugging,and experiments in a lake,the results show that the real-time parallel processing system has good stability and real-time processing capability and meets the technical design requirements of real-time processing.展开更多
The flexibility of traditional image processing system is limited because those system are designed for specific applications. In this paper, a new TMS320C64x-based multi-DSP parallel computing architecture is present...The flexibility of traditional image processing system is limited because those system are designed for specific applications. In this paper, a new TMS320C64x-based multi-DSP parallel computing architecture is presented. It has many promising characteristics such as powerful computing capability, broad I/O bandwidth, topology flexibility, and expansibility. The parallel system performance is evaluated by practical experiment.展开更多
为解决语音增强任务中语音信息未充分利用的问题,提出一种基于深度学习的方法,即融合精确比值掩蔽的门控扩张循环卷积神经网络(gate-dilated recurrent convolutional neural network with accurate ratio masking, GDRCNN-ARM)。GDRCN...为解决语音增强任务中语音信息未充分利用的问题,提出一种基于深度学习的方法,即融合精确比值掩蔽的门控扩张循环卷积神经网络(gate-dilated recurrent convolutional neural network with accurate ratio masking, GDRCNN-ARM)。GDRCNN由编码器、循环卷积层和解码器3部分组成,编码器中借助扩张卷积和门控机制实现对上下文语音信息的捕获,进行并行处理;循环卷积层采用GRU且引入多头注意力机制,捕捉网络中的长期依赖关系;解码器采用逐层解码且通过跳跃连接进行编码器信息的复用,实现对语音细节的还原。实验数据表明,GDRCNN网络在参数量和模型大小方面明显优于DNN、CRN等网络,PESQ平均提高了0.612、0.158,STOI平均提高了0.072、0.020,在语音增强和泛化方面表现出色。展开更多
This paper presents partially asynchronous parallel simulation of continuous-system (PAPSoCS) and some approaches to the issues of its implementation on a multicomputer system. To guarantee the simulation results cor...This paper presents partially asynchronous parallel simulation of continuous-system (PAPSoCS) and some approaches to the issues of its implementation on a multicomputer system. To guarantee the simulation results correct and speedup the simulation, the scheme for efficient PAPSoCS is proposed and the virtual topology star is constructed to match the path of message passing for solving algorithm-architecture adequation problem. Under the circumstances that messages frequently passed inter-processor are much shorter, typically within several 4 bytes, asynchronous communication mode is employed to reduce the communication ratio. Experiment results show that asynchronous parallel simulation has much higher efficiency than its synchronous counterpart.展开更多
This paper takes the Sobel operator as example to study parallel sequential algorithm onto a memory-sharing multiprocessor by using a virtual machine. Several different parallel algorithms using function decomposition...This paper takes the Sobel operator as example to study parallel sequential algorithm onto a memory-sharing multiprocessor by using a virtual machine. Several different parallel algorithms using function decomposition and/or data decomposition methods are compared and their performances are analyzed in terms of processor utilization, data traffic, shared memory access, and synchronization overhead. The analysis is validated through a simulation experiment on the virtual machine of 64 parallel processors. Conclusions are presented at the end of this paper.展开更多
A systolic array architecture computer (FXCQ) has been designed for signal processing. R can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that are connected linearly...A systolic array architecture computer (FXCQ) has been designed for signal processing. R can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that are connected linearly and form a ring structure. All processing cells are identical and programmable. Each processing cell has the peak performance of 20 million floating-point operations per second (20MFLOPS). The machine therefore has a peak performance of 320 M FLOPS. It is integrated as an attached processor into a host system through VME bus interface. Programs for FXCQ are written in a high-level language -B language, which is supported by a parallel optimizing compiler. This paper describes the architecture of FXCQ, B language and its compiler.展开更多
Parallel versions of prestack KirchhofT 3D integral migration algorithm, which is suitable forseismic data processing, are described in this paper. Firstly, the inherent parallel characteristics of seismicdata process...Parallel versions of prestack KirchhofT 3D integral migration algorithm, which is suitable forseismic data processing, are described in this paper. Firstly, the inherent parallel characteristics of seismicdata processing are analyzed. Then some principles in algorithm partition are discussed. Based on these analyses and the system architecture, communication mechanism, this algorithm is divided into four subtasksallocated to four nodes of 990 STAR-l. Then we describe in detail a module-partitioning method-theI / O processing and communication are separated from the computation process, the processes includingI / O processing and communication are allocated to transputer T805 and the other is allocated to processori860. These two processes are synchronized by shared memory and memory-lock mechanism, but the communication betWeen different nodes is implemented through links of transputer. Load balance among fourprocessor modules is performed dynamically. Finally, we discussed the speed--up of the parallel versions ofprestack KirchhofT 3D integral migration algorithm running on four nodes. Some further researches are also melltioned in this paper.展开更多
基金Sponsored by National Natural Science Foundation of China(60572098)
文摘ADSP-TS101 is a high performance DSP with good properties of parallel processing and high speed.According to the real-time processing requirements of underwater acoustic communication algorithms,a real-time parallel processing system with multi-channel synchronous sample,which is composed of multiple ADSP-TS101s,is designed and carried out.For the hardware design,field programmable gate array(FPGA)logical control is adopted for the design of multi-channel synchronous sample module and cluster/data flow associated pin connection mode is adopted for multiprocessing parallel processing configuration respectively.And the software is optimized by two kinds of communication ways:broadcast writing way through shared bus and point-to-point way through link ports.Through the whole system installation,connective debugging,and experiments in a lake,the results show that the real-time parallel processing system has good stability and real-time processing capability and meets the technical design requirements of real-time processing.
基金This project was supported by the National Natural Science Foundation of China (60135020).
文摘The flexibility of traditional image processing system is limited because those system are designed for specific applications. In this paper, a new TMS320C64x-based multi-DSP parallel computing architecture is presented. It has many promising characteristics such as powerful computing capability, broad I/O bandwidth, topology flexibility, and expansibility. The parallel system performance is evaluated by practical experiment.
文摘为解决语音增强任务中语音信息未充分利用的问题,提出一种基于深度学习的方法,即融合精确比值掩蔽的门控扩张循环卷积神经网络(gate-dilated recurrent convolutional neural network with accurate ratio masking, GDRCNN-ARM)。GDRCNN由编码器、循环卷积层和解码器3部分组成,编码器中借助扩张卷积和门控机制实现对上下文语音信息的捕获,进行并行处理;循环卷积层采用GRU且引入多头注意力机制,捕捉网络中的长期依赖关系;解码器采用逐层解码且通过跳跃连接进行编码器信息的复用,实现对语音细节的还原。实验数据表明,GDRCNN网络在参数量和模型大小方面明显优于DNN、CRN等网络,PESQ平均提高了0.612、0.158,STOI平均提高了0.072、0.020,在语音增强和泛化方面表现出色。
文摘This paper presents partially asynchronous parallel simulation of continuous-system (PAPSoCS) and some approaches to the issues of its implementation on a multicomputer system. To guarantee the simulation results correct and speedup the simulation, the scheme for efficient PAPSoCS is proposed and the virtual topology star is constructed to match the path of message passing for solving algorithm-architecture adequation problem. Under the circumstances that messages frequently passed inter-processor are much shorter, typically within several 4 bytes, asynchronous communication mode is employed to reduce the communication ratio. Experiment results show that asynchronous parallel simulation has much higher efficiency than its synchronous counterpart.
文摘This paper takes the Sobel operator as example to study parallel sequential algorithm onto a memory-sharing multiprocessor by using a virtual machine. Several different parallel algorithms using function decomposition and/or data decomposition methods are compared and their performances are analyzed in terms of processor utilization, data traffic, shared memory access, and synchronization overhead. The analysis is validated through a simulation experiment on the virtual machine of 64 parallel processors. Conclusions are presented at the end of this paper.
文摘A systolic array architecture computer (FXCQ) has been designed for signal processing. R can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that are connected linearly and form a ring structure. All processing cells are identical and programmable. Each processing cell has the peak performance of 20 million floating-point operations per second (20MFLOPS). The machine therefore has a peak performance of 320 M FLOPS. It is integrated as an attached processor into a host system through VME bus interface. Programs for FXCQ are written in a high-level language -B language, which is supported by a parallel optimizing compiler. This paper describes the architecture of FXCQ, B language and its compiler.
文摘Parallel versions of prestack KirchhofT 3D integral migration algorithm, which is suitable forseismic data processing, are described in this paper. Firstly, the inherent parallel characteristics of seismicdata processing are analyzed. Then some principles in algorithm partition are discussed. Based on these analyses and the system architecture, communication mechanism, this algorithm is divided into four subtasksallocated to four nodes of 990 STAR-l. Then we describe in detail a module-partitioning method-theI / O processing and communication are separated from the computation process, the processes includingI / O processing and communication are allocated to transputer T805 and the other is allocated to processori860. These two processes are synchronized by shared memory and memory-lock mechanism, but the communication betWeen different nodes is implemented through links of transputer. Load balance among fourprocessor modules is performed dynamically. Finally, we discussed the speed--up of the parallel versions ofprestack KirchhofT 3D integral migration algorithm running on four nodes. Some further researches are also melltioned in this paper.
基金Supported by National Natural Science Foundation of China（60474035）,National Research Foundation for the Doctoral Program of Higher Education of China（20050359004）,Natural Science Foundation of Anhui Province（070412035）
