InGaAs high electron mobility transistors （HEMTs） on InP substrate with very good device performance have been grown by mental organic chemical vapor deposition （MOCVD）. Room temperature Hall mobilities of the 2-D...InGaAs high electron mobility transistors （HEMTs） on InP substrate with very good device performance have been grown by mental organic chemical vapor deposition （MOCVD）. Room temperature Hall mobilities of the 2-DEG are measured to be over 8 700 cm^2/V-s with sheet carrier densities larger than 4.6× 10^12 cm^ 2. Transistors with 1.0 μm gate length exhibits transconductance up to 842 mS/ram. Excellent depletion-mode operation, with a threshold voltage of-0.3 V and IDss of 673 mA/mm, is realized. The non-alloyed ohmic contact special resistance is as low as 1.66×10^-8 Ω/cm^2, which is so far the lowest ohmic contact special resistance. The unity current gain cut off frequency （fT） and the maximum oscillation frequency （fmax） are 42.7 and 61.3 GHz, respectively. These results are very encouraging toward manufacturing InP-based HEMT by MOCVD.展开更多
Organic thin film transistors (OTFTs) have attracted much attention in low-cost, large area wearable electronics in the recent years[1-3]. The electrical stability performance of these devices under stretching is crit...Organic thin film transistors (OTFTs) have attracted much attention in low-cost, large area wearable electronics in the recent years[1-3]. The electrical stability performance of these devices under stretching is critical for applications in wearable electronics[4].Organic semiconductors have been widely used for wearable electronics due to their electrical properties of intrinsic materials and the mechanical properties of organic compounds, which can be deposited with low-cost solution processed techniques.展开更多
The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents...The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling(BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel(or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si_3N_4 tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope(Ss) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.展开更多
The tunnel field-effect transistor(TFET) is a potential candidate for the post-CMOS era.As one of the most important electrical parameters of a device,double gate TFET(DG-TFET) gate threshold voltage was studied.First...The tunnel field-effect transistor(TFET) is a potential candidate for the post-CMOS era.As one of the most important electrical parameters of a device,double gate TFET(DG-TFET) gate threshold voltage was studied.First,a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported.Then,a simple analytical model for DG-TFET gate threshold voltage VTG was built by solving quasi-two-dimensional Poisson equation in Si film.The model as a function of the drain voltage,the Si layer thickness,the gate length and the gate dielectric was discussed.It is shown that the proposed model is consistent with the simulation results.This model should be useful for further investigation of performance of circuits containing TFETs.展开更多
A novel grain boundary(GB) model characterized with different angles and positions in the nanowire was set up.By means of device simulator,the effects of grain boundary angle and location on the electrical performance...A novel grain boundary(GB) model characterized with different angles and positions in the nanowire was set up.By means of device simulator,the effects of grain boundary angle and location on the electrical performance of ZnO nanowire FET(Nanowire Field-Effect Transistor) with a wrap-around gate configuration,were explored.With the increase of the grain boundary angle,the electrical performance degrades gradually.When a grain boundary with a smaller angle,such as 5° GB,is located close to the source or drain electrode,the grain boundary is partially depleted by an electric field peak,which leads to the decrease of electron concentration and the degradation of transistor characteristics.When the 90° GB is located at the center of the nanowire,the action of the electric field is balanced out,so the electrical performance of transistor is better than that of the 90° GB located at the other positions.展开更多
基金Project(Z132012A001)supported by the Technical Basis Research Program in Science and Industry Bureau of ChinaProject(61201028,60876009)supported by the National Natural Science Foundation of China
文摘InGaAs high electron mobility transistors （HEMTs） on InP substrate with very good device performance have been grown by mental organic chemical vapor deposition （MOCVD）. Room temperature Hall mobilities of the 2-DEG are measured to be over 8 700 cm^2/V-s with sheet carrier densities larger than 4.6× 10^12 cm^ 2. Transistors with 1.0 μm gate length exhibits transconductance up to 842 mS/ram. Excellent depletion-mode operation, with a threshold voltage of-0.3 V and IDss of 673 mA/mm, is realized. The non-alloyed ohmic contact special resistance is as low as 1.66×10^-8 Ω/cm^2, which is so far the lowest ohmic contact special resistance. The unity current gain cut off frequency （fT） and the maximum oscillation frequency （fmax） are 42.7 and 61.3 GHz, respectively. These results are very encouraging toward manufacturing InP-based HEMT by MOCVD.
文摘Organic thin film transistors (OTFTs) have attracted much attention in low-cost, large area wearable electronics in the recent years[1-3]. The electrical stability performance of these devices under stretching is critical for applications in wearable electronics[4].Organic semiconductors have been widely used for wearable electronics due to their electrical properties of intrinsic materials and the mechanical properties of organic compounds, which can be deposited with low-cost solution processed techniques.
基金Projects(61574109,61204092)supported by the National Natural Science Foundation of China
文摘The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling(BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel(or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si_3N_4 tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope(Ss) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.
基金Project(P140c090303110c0904)supported by NLAIC Research Fund,ChinaProject(JY0300122503)supported by the Research Fund for the Doctoral Program of Higher Education of China+1 种基金Projects(K5051225014,K5051225004)supported by the Fundamental Research Funds for the Central Universities,ChinaProject(2010JQ8008)supported by the Natural Science Basic Research Plan in Shaanxi Province of China
文摘The tunnel field-effect transistor(TFET) is a potential candidate for the post-CMOS era.As one of the most important electrical parameters of a device,double gate TFET(DG-TFET) gate threshold voltage was studied.First,a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported.Then,a simple analytical model for DG-TFET gate threshold voltage VTG was built by solving quasi-two-dimensional Poisson equation in Si film.The model as a function of the drain voltage,the Si layer thickness,the gate length and the gate dielectric was discussed.It is shown that the proposed model is consistent with the simulation results.This model should be useful for further investigation of performance of circuits containing TFETs.
基金Project(60876022) supported by the National Natural Science Foundation of ChinaProject(50925727) supported by the National Natural Science Funds for Distinguished Young Scholars of China
文摘A novel grain boundary(GB) model characterized with different angles and positions in the nanowire was set up.By means of device simulator,the effects of grain boundary angle and location on the electrical performance of ZnO nanowire FET(Nanowire Field-Effect Transistor) with a wrap-around gate configuration,were explored.With the increase of the grain boundary angle,the electrical performance degrades gradually.When a grain boundary with a smaller angle,such as 5° GB,is located close to the source or drain electrode,the grain boundary is partially depleted by an electric field peak,which leads to the decrease of electron concentration and the degradation of transistor characteristics.When the 90° GB is located at the center of the nanowire,the action of the electric field is balanced out,so the electrical performance of transistor is better than that of the 90° GB located at the other positions.
