This paper presents a hardware architecture using mixed pipeline and parallel processing for complex division based on dichotomous coordinate descent(DCD) iterations. The objective of the proposed work is to achieve l...This paper presents a hardware architecture using mixed pipeline and parallel processing for complex division based on dichotomous coordinate descent(DCD) iterations. The objective of the proposed work is to achieve low-latency and resource optimized complex divider architecture in adaptive weight computation stage of minimum variance distortionless response(MVDR)algorithm. In this work, computation of complex division is modeled as a 2×2 linear equation solution problem and the DCD algorithm allows linear systems of equations to be solved with high degree of computational efficiency. The operations in the existing DCD algorithm are suitably parallel pipelined and the performance is optimized to 2 clock cycles per iteration. To improve the degree of parallelism, a parallel column vector read architecture is devised.The proposed work is implemented on the field programmable gate array(FPGA) platform and the results are compared with state-of-art literature. It concludes that the proposed architecture is suitable for complex division in adaptive weight computation stage of MVDR beamformer. We demonstrate the performance of the proposed architecture for MVDR beamformer employed in medical ultrasound imaging applications.展开更多
目标方位估计(Direction of arrival,DOA)和信号恢复分别是水下目标定位、跟踪与识别的前提.基于盲源分离方法可以得到含有阵列流形信息的解混矩阵,融合成熟的高分辨方法提出了一种新的方位估计、信号恢复模型和方法.在宽带信号背景下...目标方位估计(Direction of arrival,DOA)和信号恢复分别是水下目标定位、跟踪与识别的前提.基于盲源分离方法可以得到含有阵列流形信息的解混矩阵,融合成熟的高分辨方法提出了一种新的方位估计、信号恢复模型和方法.在宽带信号背景下进行了仿真实验,结果表明该方法可实现目标方位的实时估计和目标信号的恢复.在同等条件下完成同样的目标方位分辨率,比单纯的高分辨方法要求的阵元数和快拍数较少,要求的信噪比要低.海上实测数据检验也表明,比常规的最小方差无失真响应(Minimum variance distortionless response,MVDR)方法得到了更好的结果,明显提高了弱目标信号的空间谱能量,增强了检测弱目标信号的能力.展开更多
基金supported by Microelectronics Division of the Ministry of Electronics and Information Technology,Government of India,under SMDP-C2SD Project(9(1)/2014–MDD)
文摘This paper presents a hardware architecture using mixed pipeline and parallel processing for complex division based on dichotomous coordinate descent(DCD) iterations. The objective of the proposed work is to achieve low-latency and resource optimized complex divider architecture in adaptive weight computation stage of minimum variance distortionless response(MVDR)algorithm. In this work, computation of complex division is modeled as a 2×2 linear equation solution problem and the DCD algorithm allows linear systems of equations to be solved with high degree of computational efficiency. The operations in the existing DCD algorithm are suitably parallel pipelined and the performance is optimized to 2 clock cycles per iteration. To improve the degree of parallelism, a parallel column vector read architecture is devised.The proposed work is implemented on the field programmable gate array(FPGA) platform and the results are compared with state-of-art literature. It concludes that the proposed architecture is suitable for complex division in adaptive weight computation stage of MVDR beamformer. We demonstrate the performance of the proposed architecture for MVDR beamformer employed in medical ultrasound imaging applications.
