为研究异构多核片上系统(multi-processor system on chip,MPSoC)在密集并行计算任务中的潜力,文章设计并实现了一种适用于粗粒度数据特征、面向任务级并行应用的异构多核系统动态调度协处理器,采用了片上缓存、任务输出的多级写回管理...为研究异构多核片上系统(multi-processor system on chip,MPSoC)在密集并行计算任务中的潜力,文章设计并实现了一种适用于粗粒度数据特征、面向任务级并行应用的异构多核系统动态调度协处理器,采用了片上缓存、任务输出的多级写回管理、任务自动映射、通讯任务乱序执行等机制。实验结果表明,该动态调度协处理器不仅能够实现任务级乱序执行等基本设计目标,还具有极低的调度开销,相较于基于动态记分牌算法的调度器,运行多个子孔径距离压缩算法的时间降低达17.13%。研究结果证明文章设计的动态调度协处理器能够有效优化目标场景下的任务调度效果。展开更多
The paper presents a parallel ATPG algorithm - PTGBP, which aims at decreasing the complexity of the ATPG by partitioning circuit under test (CUT) to big function blocks (BFB) and processing them parallelly. PTGBP ado...The paper presents a parallel ATPG algorithm - PTGBP, which aims at decreasing the complexity of the ATPG by partitioning circuit under test (CUT) to big function blocks (BFB) and processing them parallelly. PTGBP adopts hybrid circuit mode and hybrid fault model, and organizes the parallel course in term of master/slave mode. Master processor loads the whole netlist of CUT based on BFB, every slave processor loads logic level (gate/function block/basic logic units) netlist of a BFB. Test generation (TG) uses BFB input/output s-a-0/s-a-1 fault model; fault simulation uses logic level single stuck fault model. Master controls the PTGBP’s running course and ensures the correctness of its running result; slaves provide the results of fault sensitization compatible computation and fault simulation to master parallelly. PTGBP algorithm is under implementation.展开更多
文摘为研究异构多核片上系统(multi-processor system on chip,MPSoC)在密集并行计算任务中的潜力,文章设计并实现了一种适用于粗粒度数据特征、面向任务级并行应用的异构多核系统动态调度协处理器,采用了片上缓存、任务输出的多级写回管理、任务自动映射、通讯任务乱序执行等机制。实验结果表明,该动态调度协处理器不仅能够实现任务级乱序执行等基本设计目标,还具有极低的调度开销,相较于基于动态记分牌算法的调度器,运行多个子孔径距离压缩算法的时间降低达17.13%。研究结果证明文章设计的动态调度协处理器能够有效优化目标场景下的任务调度效果。
基金Supported by National Natural Science Founding of China.
文摘The paper presents a parallel ATPG algorithm - PTGBP, which aims at decreasing the complexity of the ATPG by partitioning circuit under test (CUT) to big function blocks (BFB) and processing them parallelly. PTGBP adopts hybrid circuit mode and hybrid fault model, and organizes the parallel course in term of master/slave mode. Master processor loads the whole netlist of CUT based on BFB, every slave processor loads logic level (gate/function block/basic logic units) netlist of a BFB. Test generation (TG) uses BFB input/output s-a-0/s-a-1 fault model; fault simulation uses logic level single stuck fault model. Master controls the PTGBP’s running course and ensures the correctness of its running result; slaves provide the results of fault sensitization compatible computation and fault simulation to master parallelly. PTGBP algorithm is under implementation.
