In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC...In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.展开更多
为简化Turbo乘积码(Turbo Product Code,TPC)译码处理过程,缩短接收机译码时延,针对航天测控领域应用广泛的子码为扩展汉明码的TPC码,提出一种改进的混合译码算法。改进算法以传统混合译码算法为基础,把SISO和HIHO两种译码器相结合,优...为简化Turbo乘积码(Turbo Product Code,TPC)译码处理过程,缩短接收机译码时延,针对航天测控领域应用广泛的子码为扩展汉明码的TPC码,提出一种改进的混合译码算法。改进算法以传统混合译码算法为基础,把SISO和HIHO两种译码器相结合,优化软输入输出(Soft In Soft Out,SISO)中的外信息计算方式,纠正硬输入输出(Hard In Hard Out,HIHO)中的特殊错误图样,并引入切换门限完成SISO到HIHO的自适应切换,实现了基于码字可靠性的智能译码。仿真表明,对于TPC码(64,57)2,误码率为10-5时,改进算法在不减弱译码性能的前提下,复杂度仅为原算法的1/2。改进算法的提出及应用,将有利于航天测控设备小型化和国产化。展开更多
文摘In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.
文摘为简化Turbo乘积码(Turbo Product Code,TPC)译码处理过程,缩短接收机译码时延,针对航天测控领域应用广泛的子码为扩展汉明码的TPC码,提出一种改进的混合译码算法。改进算法以传统混合译码算法为基础,把SISO和HIHO两种译码器相结合,优化软输入输出(Soft In Soft Out,SISO)中的外信息计算方式,纠正硬输入输出(Hard In Hard Out,HIHO)中的特殊错误图样,并引入切换门限完成SISO到HIHO的自适应切换,实现了基于码字可靠性的智能译码。仿真表明,对于TPC码(64,57)2,误码率为10-5时,改进算法在不减弱译码性能的前提下,复杂度仅为原算法的1/2。改进算法的提出及应用,将有利于航天测控设备小型化和国产化。
