A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchr...A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.展开更多
The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automati...The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)展开更多
A binary tree representation is designed in this paper for optimization of wave digital filter（WDF）implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree repres...A binary tree representation is designed in this paper for optimization of wave digital filter（WDF）implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree representation at first.This WDF binary tree can then be transformed to several topologies with the same implication,since the WDF adaptors have a symmetrical behavior on their ports.Because the WDF implementation is related to field programmable gate array（FPGA）resource usage and the cycle time of emulation,choosing aproper binary tree topology for WDF implementation can help balance the complexity and performance quality of an emulation system.Both WDF-FPGA emulation and HSpice simulation on the same circuit are tested.There is no significant difference between these two simulations.However,in terms of time consumption,the WDF-FPGA emulation has an advantage over the other.Our experiment also demonstrates that the optimized WDF-FPGA emulation has an acceptable accuracy and feasibility.展开更多
A novel efficient partial sharing channelization structure with odd and even stacking is designed and implemented. There are two special designs in the proposed structure. Firstly, by the intensive channel overlap des...A novel efficient partial sharing channelization structure with odd and even stacking is designed and implemented. There are two special designs in the proposed structure. Firstly, by the intensive channel overlap design, for non-cooperative wideband signals, the proposed structure can achieve good parameter estimation accuracy and high probability of complete interception.Secondly, based on the partial sharing design developed in this paper, the computation burden of the proposed structure can be greatly reduced compared with the traditional directly implemented structures. Experiments and numerical simulations are conducted to evaluate the proposed structure, which shows its improvements over traditional methods in terms of field programmable gate arrays(FPGA) resource consumption and parameter estimation accuracy.展开更多
Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is co...Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is constructed.The dynamics characteristics including bifurcation behavior and coexistence of the system are analyzed in detail,the latter reveals abundant coexisting flows.Furthermore,the proposed system passes the NIST tests and has been implemented physically by FPGA.Compared to the multi-scroll dissipative chaos,the experimental portraits of the proposed system show better ergodicity,which have potential application value in secure communication and image encryption.展开更多
Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for...Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.展开更多
针对CAN(Controller Area Network)总线网络物理传输性能测试的需要,提出一种基于FPGA(FieldProgrammable Gate Array)测试系统,该系统通过采集物理层信号波形分析CAN总线故障并输出相关信息。分析了测试系统原理,给出了系统方案,并详...针对CAN(Controller Area Network)总线网络物理传输性能测试的需要,提出一种基于FPGA(FieldProgrammable Gate Array)测试系统,该系统通过采集物理层信号波形分析CAN总线故障并输出相关信息。分析了测试系统原理,给出了系统方案,并详细论述了频率的自动识别、数据帧提取、总线故障分析、数据存储等关键技术的实现方法。对测试系统进行了功能仿真,并在搭建的测试平台上进行了测试。仿真和测试结果表明,该系统能正确识别总线故障,并输出相关信息。展开更多
基金the Natural Science Foundation of Hubei Province (No.2005ABA301)
文摘A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.
文摘The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)
基金Supported by the National Natural Science Foundation of China(61271113)
文摘A binary tree representation is designed in this paper for optimization of wave digital filter（WDF）implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree representation at first.This WDF binary tree can then be transformed to several topologies with the same implication,since the WDF adaptors have a symmetrical behavior on their ports.Because the WDF implementation is related to field programmable gate array（FPGA）resource usage and the cycle time of emulation,choosing aproper binary tree topology for WDF implementation can help balance the complexity and performance quality of an emulation system.Both WDF-FPGA emulation and HSpice simulation on the same circuit are tested.There is no significant difference between these two simulations.However,in terms of time consumption,the WDF-FPGA emulation has an advantage over the other.Our experiment also demonstrates that the optimized WDF-FPGA emulation has an acceptable accuracy and feasibility.
文摘A novel efficient partial sharing channelization structure with odd and even stacking is designed and implemented. There are two special designs in the proposed structure. Firstly, by the intensive channel overlap design, for non-cooperative wideband signals, the proposed structure can achieve good parameter estimation accuracy and high probability of complete interception.Secondly, based on the partial sharing design developed in this paper, the computation burden of the proposed structure can be greatly reduced compared with the traditional directly implemented structures. Experiments and numerical simulations are conducted to evaluate the proposed structure, which shows its improvements over traditional methods in terms of field programmable gate arrays(FPGA) resource consumption and parameter estimation accuracy.
基金Project supported by the Natural Science Foundation of Tianjin,China(Grant No.18JCYBJC87700)the Natural Science Foundation of China(Grant No.61603274)。
文摘Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is constructed.The dynamics characteristics including bifurcation behavior and coexistence of the system are analyzed in detail,the latter reveals abundant coexisting flows.Furthermore,the proposed system passes the NIST tests and has been implemented physically by FPGA.Compared to the multi-scroll dissipative chaos,the experimental portraits of the proposed system show better ergodicity,which have potential application value in secure communication and image encryption.
基金financially supported by the National Council for Scientific and Technological Development(CNPq,Brazil),Swedish-Brazilian Research and Innovation Centre(CISB),and Saab AB under Grant No.CNPq:200053/2022-1the National Council for Scientific and Technological Development(CNPq,Brazil)under Grants No.CNPq:312924/2017-8 and No.CNPq:314660/2020-8.
文摘Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.
文摘针对CAN(Controller Area Network)总线网络物理传输性能测试的需要,提出一种基于FPGA(FieldProgrammable Gate Array)测试系统,该系统通过采集物理层信号波形分析CAN总线故障并输出相关信息。分析了测试系统原理,给出了系统方案,并详细论述了频率的自动识别、数据帧提取、总线故障分析、数据存储等关键技术的实现方法。对测试系统进行了功能仿真,并在搭建的测试平台上进行了测试。仿真和测试结果表明,该系统能正确识别总线故障,并输出相关信息。
