An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer （ DDS ） -driven wideband phase-locked loop （PLL） architecture which...An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer （ DDS ） -driven wideband phase-locked loop （PLL） architecture which can achieve low spurious noise and rapid frequency hopping simultaneous- ly. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor （DAC） output is analyzed. A novel DDS frequency planning method is proposed to ensure low col- ored noise within the entire bandwidth. The designed output frequency range is 3. 765 -4. 085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range （SFDR） is about 64 dBc in a 320 MHz bandwidth.展开更多
基金Supported by the Fund of National Defense Industry Innova-tive Team(231)
文摘An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer （ DDS ） -driven wideband phase-locked loop （PLL） architecture which can achieve low spurious noise and rapid frequency hopping simultaneous- ly. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor （DAC） output is analyzed. A novel DDS frequency planning method is proposed to ensure low col- ored noise within the entire bandwidth. The designed output frequency range is 3. 765 -4. 085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range （SFDR） is about 64 dBc in a 320 MHz bandwidth.
