本文主要研究高性能FPGA可编程逻辑单元中分布式RAM和移位寄存器两种时序功能的设计实现方法.运用静态Latch实现分布式RAM的写入同步,以降低对时序控制电路的要求;为克服电荷共享问题,提出通过隔断存储单元之间通路的方法实现移位寄存器...本文主要研究高性能FPGA可编程逻辑单元中分布式RAM和移位寄存器两种时序功能的设计实现方法.运用静态Latch实现分布式RAM的写入同步,以降低对时序控制电路的要求;为克服电荷共享问题,提出通过隔断存储单元之间通路的方法实现移位寄存器.以含两个四输入LUT(Look Up Table)的多功能可编程逻辑单元为例,详细说明电路的设计思路以及实现方法.研究表明,本文提出的方法可以简化对时序控制电路的设计要求,克服电荷共享问题,减少芯片面积.展开更多
Field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/soft...Field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software （HW/SW） co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block （IOB） and configurable logic block （CLB） of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.展开更多
A novel test approach for interconnect resources （IRs） in field programmable gate arrays （FPGA） has been proposed.In the test approach,SBs （switch boxes） of IRs in FPGA has been utilized to test IRs.Furthermore,...A novel test approach for interconnect resources （IRs） in field programmable gate arrays （FPGA） has been proposed.In the test approach,SBs （switch boxes） of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks （CLBs） in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip （SoC） hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.展开更多
文摘本文主要研究高性能FPGA可编程逻辑单元中分布式RAM和移位寄存器两种时序功能的设计实现方法.运用静态Latch实现分布式RAM的写入同步,以降低对时序控制电路的要求;为克服电荷共享问题,提出通过隔断存储单元之间通路的方法实现移位寄存器.以含两个四输入LUT(Look Up Table)的多功能可编程逻辑单元为例,详细说明电路的设计思路以及实现方法.研究表明,本文提出的方法可以简化对时序控制电路的设计要求,克服电荷共享问题,减少芯片面积.
基金supported by Key Techniques of FPGA Architecture under Grant No.9140A08010106QT9201the support from UESTC Youth Funds
文摘Field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software （HW/SW） co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block （IOB） and configurable logic block （CLB） of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.
基金supported by the Key Techniques of FPGA Architecture under Grant No. 9140A08010106QT9201
文摘A novel test approach for interconnect resources （IRs） in field programmable gate arrays （FPGA） has been proposed.In the test approach,SBs （switch boxes） of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks （CLBs） in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip （SoC） hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.
