In order to research the effects of built-in test(BIT) on the system and select BITand test strategy,the complex repairable systems with BITequipment are modeled and simulated by using Simulink.Based on the model,the ...In order to research the effects of built-in test(BIT) on the system and select BITand test strategy,the complex repairable systems with BITequipment are modeled and simulated by using Simulink.Based on the model,the influences of different built-in test equipments,maintenance time and error probabilities on the system usability are evaluated.The simulation results showthat they effect on the system differently.The simulation method of complex system based on Simulink provides a technique approach to research the effects of BITon the system and select BITand test strategy.展开更多
A novel built-in self-test （BIST） approach to test the configurable input/output buffers in Xilinx Virtex series SoCs （system on a chip） using hard macro has been proposed in this paper. The proposed approach can ...A novel built-in self-test （BIST） approach to test the configurable input/output buffers in Xilinx Virtex series SoCs （system on a chip） using hard macro has been proposed in this paper. The proposed approach can completely detect single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series FPGAs （field programmable gate configurations are required array）. Only total of 10 to completely test the I/O buffers of Virtex devices.展开更多
文摘In order to research the effects of built-in test(BIT) on the system and select BITand test strategy,the complex repairable systems with BITequipment are modeled and simulated by using Simulink.Based on the model,the influences of different built-in test equipments,maintenance time and error probabilities on the system usability are evaluated.The simulation results showthat they effect on the system differently.The simulation method of complex system based on Simulink provides a technique approach to research the effects of BITon the system and select BITand test strategy.
基金supported by the 44th China Postdoctoral Science Foundation funded project
文摘A novel built-in self-test （BIST） approach to test the configurable input/output buffers in Xilinx Virtex series SoCs （system on a chip） using hard macro has been proposed in this paper. The proposed approach can completely detect single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series FPGAs （field programmable gate configurations are required array）. Only total of 10 to completely test the I/O buffers of Virtex devices.
