To generate a test set for a given circuit (including both combinational and sequential circuits), choice of an algorithm within a number of existing test generation algorithms to apply is bound to vary from circuit t...To generate a test set for a given circuit (including both combinational and sequential circuits), choice of an algorithm within a number of existing test generation algorithms to apply is bound to vary from circuit to circuit. In this paper, the genetic algorithms are used to construct the models of existing test generation algorithms in making such choice more easily. Therefore, we may forecast the testability parameters of a circuit before using the real test generation algorithm. The results also can be used to evaluate the efficiency of the existing test generation algorithms. Experimental results are given to convince the readers of the truth and the usefulness of this approach.展开更多
To study the diagnostic problem of Wire-OR （W-O） interconnect fault of PCB （Printed Circuit Board）, five modified boundary scan adaptive algorithms for interconnect test are put forward. These algorithms apply Glo...To study the diagnostic problem of Wire-OR （W-O） interconnect fault of PCB （Printed Circuit Board）, five modified boundary scan adaptive algorithms for interconnect test are put forward. These algorithms apply Global-diagnosis sequence algorithm to replace the equal weight algorithm of primary test, and the test time is shortened without changing the fault diagnostic capability. The descriptions of five modified adaptive test algorithms are presented, and the capability comparison between the modified algorithm and the original algorithm is made to prove the validity of these algorithms.展开更多
This paper deals with the target-fault-oriented test generation of sequential circuits using genetic algorithms. We adopted the concept of multiple phases and proposed four sub-procedures which consist of activation, ...This paper deals with the target-fault-oriented test generation of sequential circuits using genetic algorithms. We adopted the concept of multiple phases and proposed four sub-procedures which consist of activation, propagation and justification phases. The paper focuses on the design of genetic operators and construction of fitness functions which are based on the structure information of circuits. Using ISCAS89 benchmarks, the experiment results of GA were given.展开更多
A novel multi-chip module(MCM) interconnect test generation scheme based on ant algorithm(AA) with mutation operator was presented.By combing the characteristics of MCM interconnect test generation,the pheromone updat...A novel multi-chip module(MCM) interconnect test generation scheme based on ant algorithm(AA) with mutation operator was presented.By combing the characteristics of MCM interconnect test generation,the pheromone updating rule and state transition rule of AA is designed.Using mutation operator,this scheme overcomes ordinary AA’s defects of slow convergence speed,easy to get stagnate,and low ability of full search.The international standard MCM benchmark circuit provided by the MCNC group was used to verify the approach.The results of simulation experiments,which compare to the results of standard ant algorithm,genetic algorithm(GA) and other deterministic interconnecting algorithms,show that the proposed scheme can achieve high fault coverage,compact test set and short CPU time,that it is a newer optimized method deserving research.展开更多
Based on the sequential probability ratio test(SPRT)developed by Wald,an improved method for successful probability test of missile flight is proposed.A recursive algorithm and its program in Matlab are designed to ca...Based on the sequential probability ratio test(SPRT)developed by Wald,an improved method for successful probability test of missile flight is proposed.A recursive algorithm and its program in Matlab are designed to calculate the real risk level of the sequential test decision and the average number of samples under various test conditions.A concept,that is "rejecting as soon as possible",is put forward and an alternate operation strategy is conducted.The simulation results show that it can reduce the test expenses.展开更多
智能体路径规划算法旨在规划某个智能体的行为轨迹,使其在不碰到障碍物的情况下安全且高效地从起始点到达目标点.目前智能体路径规划算法已经被广泛应用到各种重要的物理信息系统中,因此在实际投入使用前对算法进行测试,以评估其性能是...智能体路径规划算法旨在规划某个智能体的行为轨迹,使其在不碰到障碍物的情况下安全且高效地从起始点到达目标点.目前智能体路径规划算法已经被广泛应用到各种重要的物理信息系统中,因此在实际投入使用前对算法进行测试,以评估其性能是否满足需求就非常重要.然而,作为路径规划算法的输入,任务空间中威胁障碍物的分布形式复杂且多样.此外,路径规划算法在为每个测试用例规划路径时,通常需要较高的运行代价.为了提升路径规划算法的测试效率,将动态随机测试思想引入到路径规划算法中,提出了面向智能体路径规划算法的动态随机测试方法(dynamic random testing approach for intelligent agent path planning algorithms,DRT-PP).具体来说,DRT-PP对路径规划任务空间进行离散划分,并在每个子区域内引入威胁生成概率,进而构建测试剖面,该测试剖面可以作为测试策略在测试用例生成过程中使用.此外,DRT-PP在测试过程中通过动态调整测试剖面,使其逐渐优化,从而提升测试效率.实验结果显示,与随机测试及自适应随机测试相比,DRT-PP方法能够在保证测试用例多样性的同时,生成更多能够暴露被测算法性能缺陷的测试用例.展开更多
基金This work was supported by National Natural Science Foundation of China (NSFC) under the grant !No. 69873030
文摘To generate a test set for a given circuit (including both combinational and sequential circuits), choice of an algorithm within a number of existing test generation algorithms to apply is bound to vary from circuit to circuit. In this paper, the genetic algorithms are used to construct the models of existing test generation algorithms in making such choice more easily. Therefore, we may forecast the testability parameters of a circuit before using the real test generation algorithm. The results also can be used to evaluate the efficiency of the existing test generation algorithms. Experimental results are given to convince the readers of the truth and the usefulness of this approach.
文摘To study the diagnostic problem of Wire-OR （W-O） interconnect fault of PCB （Printed Circuit Board）, five modified boundary scan adaptive algorithms for interconnect test are put forward. These algorithms apply Global-diagnosis sequence algorithm to replace the equal weight algorithm of primary test, and the test time is shortened without changing the fault diagnostic capability. The descriptions of five modified adaptive test algorithms are presented, and the capability comparison between the modified algorithm and the original algorithm is made to prove the validity of these algorithms.
文摘This paper deals with the target-fault-oriented test generation of sequential circuits using genetic algorithms. We adopted the concept of multiple phases and proposed four sub-procedures which consist of activation, propagation and justification phases. The paper focuses on the design of genetic operators and construction of fitness functions which are based on the structure information of circuits. Using ISCAS89 benchmarks, the experiment results of GA were given.
文摘A novel multi-chip module(MCM) interconnect test generation scheme based on ant algorithm(AA) with mutation operator was presented.By combing the characteristics of MCM interconnect test generation,the pheromone updating rule and state transition rule of AA is designed.Using mutation operator,this scheme overcomes ordinary AA’s defects of slow convergence speed,easy to get stagnate,and low ability of full search.The international standard MCM benchmark circuit provided by the MCNC group was used to verify the approach.The results of simulation experiments,which compare to the results of standard ant algorithm,genetic algorithm(GA) and other deterministic interconnecting algorithms,show that the proposed scheme can achieve high fault coverage,compact test set and short CPU time,that it is a newer optimized method deserving research.
文摘Based on the sequential probability ratio test(SPRT)developed by Wald,an improved method for successful probability test of missile flight is proposed.A recursive algorithm and its program in Matlab are designed to calculate the real risk level of the sequential test decision and the average number of samples under various test conditions.A concept,that is "rejecting as soon as possible",is put forward and an alternate operation strategy is conducted.The simulation results show that it can reduce the test expenses.
文摘智能体路径规划算法旨在规划某个智能体的行为轨迹,使其在不碰到障碍物的情况下安全且高效地从起始点到达目标点.目前智能体路径规划算法已经被广泛应用到各种重要的物理信息系统中,因此在实际投入使用前对算法进行测试,以评估其性能是否满足需求就非常重要.然而,作为路径规划算法的输入,任务空间中威胁障碍物的分布形式复杂且多样.此外,路径规划算法在为每个测试用例规划路径时,通常需要较高的运行代价.为了提升路径规划算法的测试效率,将动态随机测试思想引入到路径规划算法中,提出了面向智能体路径规划算法的动态随机测试方法(dynamic random testing approach for intelligent agent path planning algorithms,DRT-PP).具体来说,DRT-PP对路径规划任务空间进行离散划分,并在每个子区域内引入威胁生成概率,进而构建测试剖面,该测试剖面可以作为测试策略在测试用例生成过程中使用.此外,DRT-PP在测试过程中通过动态调整测试剖面,使其逐渐优化,从而提升测试效率.实验结果显示,与随机测试及自适应随机测试相比,DRT-PP方法能够在保证测试用例多样性的同时,生成更多能够暴露被测算法性能缺陷的测试用例.
