To design approximately linear-phase complex coefficient finite impulse response （FIR） digital filters with arbitrary magnitude and group delay responses, a novel neural network approach is studied. The approach is ...To design approximately linear-phase complex coefficient finite impulse response （FIR） digital filters with arbitrary magnitude and group delay responses, a novel neural network approach is studied. The approach is based on a batch back-propagation neural network algorithm by directly minimizing the real magnitude error and phase error from the linear-phase to obtain the filter＇s coefficients. The approach can deal with both the real and complex coefficient FIR digital filters design problems. The main advantage of the proposed design method is the significant reduction in the group delay error. The effectiveness of the proposed method is illustrated with two optimal design examples.展开更多
针对利用现场可编辑门阵列(FPGA)设计有限长冲击响应(FIR)数字滤波器中如何降低硬件资源消耗、提高硬件资源利用率的问题,提出一种改进的分布式算法。该算法是将固定系数的FIR滤波器系统单位脉冲响应事先存储在查找表中,利用搜索查找表...针对利用现场可编辑门阵列(FPGA)设计有限长冲击响应(FIR)数字滤波器中如何降低硬件资源消耗、提高硬件资源利用率的问题,提出一种改进的分布式算法。该算法是将固定系数的FIR滤波器系统单位脉冲响应事先存储在查找表中,利用搜索查找表得到运算结果,而不是使用传统的硬件方式来实现乘累加运算。介绍了以Altera公司的DSP Builder软件作为设计18阶FIR数字低通滤波器设计工具的具体流程和方法。通过Simulink和硬件在环(HIL)模块的引入,将设计模块下载到FPGA,进行软硬件协同仿真,给出滤波器的性能指标的实测结果。实测结果表明,所设计的18阶分布式算法低通滤波器截止频率为5.6 k Hz,带内波动:<0.5 d B,带外抑制:>18 d B,消耗的逻辑单元数量仅为442个较同阶的传统数字滤波器小一个数量级。因此,利用分布式算法设计的滤波器不仅其性能指标能够满足设计要求,对硬件资源的使用效率也有极大的改善。展开更多
基金supported by the National Natural Science Foundation of China(6087602250677014)+2 种基金the High-Tech Research and Development Program of China(2006AA04A104)the Hunan Provincial Natural Science Foundation of China (06JJ202407JJ5076).
文摘To design approximately linear-phase complex coefficient finite impulse response （FIR） digital filters with arbitrary magnitude and group delay responses, a novel neural network approach is studied. The approach is based on a batch back-propagation neural network algorithm by directly minimizing the real magnitude error and phase error from the linear-phase to obtain the filter＇s coefficients. The approach can deal with both the real and complex coefficient FIR digital filters design problems. The main advantage of the proposed design method is the significant reduction in the group delay error. The effectiveness of the proposed method is illustrated with two optimal design examples.
文摘针对利用现场可编辑门阵列(FPGA)设计有限长冲击响应(FIR)数字滤波器中如何降低硬件资源消耗、提高硬件资源利用率的问题,提出一种改进的分布式算法。该算法是将固定系数的FIR滤波器系统单位脉冲响应事先存储在查找表中,利用搜索查找表得到运算结果,而不是使用传统的硬件方式来实现乘累加运算。介绍了以Altera公司的DSP Builder软件作为设计18阶FIR数字低通滤波器设计工具的具体流程和方法。通过Simulink和硬件在环(HIL)模块的引入,将设计模块下载到FPGA,进行软硬件协同仿真,给出滤波器的性能指标的实测结果。实测结果表明,所设计的18阶分布式算法低通滤波器截止频率为5.6 k Hz,带内波动:<0.5 d B,带外抑制:>18 d B,消耗的逻辑单元数量仅为442个较同阶的传统数字滤波器小一个数量级。因此,利用分布式算法设计的滤波器不仅其性能指标能够满足设计要求,对硬件资源的使用效率也有极大的改善。
