An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generatio...An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.展开更多
As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemente...As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemented by enhancing controllability and observability. This paper discusses a non-scan testable design for a sequential circuit by only focusing the improvement of controllability. The proposed design modifies a circuit so that all the FFs can be directly controlled by primary input lines in a test mode. Experimental results show that we can get a good testability using this method.展开更多
This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overh...This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing.展开更多
This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary ...This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. Test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single Stuck-at faults), low hardware overhead and capability of at-speed test. Moreover, test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at speed of system clock.展开更多
To analyze and evaluate the testability design of equipment, a testability analysis method based on Bayesian network inference model is proposed in the paper. The model can adequately apply testability information and...To analyze and evaluate the testability design of equipment, a testability analysis method based on Bayesian network inference model is proposed in the paper. The model can adequately apply testability information and many uncertainty information of design and maintenance process, so it can analyze testability by and large from Bayesian inference. The detailed procedure to analyze and evaluate testability for equipments by Bayesian network is given in the paper. Its modeling process is simple, its formulation is visual, and the analysis results are more reliable than others. Examples prove that the analysis method based on Bayesian network inference can be applied to testability analysis and evaluation for complex equipments.展开更多
According to increase of circuitry numbers of LSI, the test application time of a full scan design method becomes one of the bottleneck problems for the LSI productivity. The test application time is corresponding to ...According to increase of circuitry numbers of LSI, the test application time of a full scan design method becomes one of the bottleneck problems for the LSI productivity. The test application time is corresponding to the test length, thus the reduction of the test length in a scan design is strongly required. In this paper, we propose a partial scan design system at RT level design, named REPS, to reduce the test application time. REPS has the following new features: (1) a scan register selection method at RT level; (2) a DFT database is prepared to estimate test length of blocks; and (3) a DFT strategy generation for the shortest test length. We applied REPS to some test designs for a practical LSI that described at RT level. It is found that REPS estimates an accurate test length for an LSI at RTL, i.e. the error of the length is less than 10% from that at the gate level. As a result, the test length generated by the partial scan design method was 37% shorter than that by the conventional full scan design method.展开更多
基金This project was supported by the National Natural Science Foundation of China (90407007).
文摘An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.
文摘As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemented by enhancing controllability and observability. This paper discusses a non-scan testable design for a sequential circuit by only focusing the improvement of controllability. The proposed design modifies a circuit so that all the FFs can be directly controlled by primary input lines in a test mode. Experimental results show that we can get a good testability using this method.
文摘This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing.
文摘This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. Test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single Stuck-at faults), low hardware overhead and capability of at-speed test. Moreover, test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at speed of system clock.
基金supported by the National Natural Science Foundation of China(60771063).
文摘To analyze and evaluate the testability design of equipment, a testability analysis method based on Bayesian network inference model is proposed in the paper. The model can adequately apply testability information and many uncertainty information of design and maintenance process, so it can analyze testability by and large from Bayesian inference. The detailed procedure to analyze and evaluate testability for equipments by Bayesian network is given in the paper. Its modeling process is simple, its formulation is visual, and the analysis results are more reliable than others. Examples prove that the analysis method based on Bayesian network inference can be applied to testability analysis and evaluation for complex equipments.
文摘According to increase of circuitry numbers of LSI, the test application time of a full scan design method becomes one of the bottleneck problems for the LSI productivity. The test application time is corresponding to the test length, thus the reduction of the test length in a scan design is strongly required. In this paper, we propose a partial scan design system at RT level design, named REPS, to reduce the test application time. REPS has the following new features: (1) a scan register selection method at RT level; (2) a DFT database is prepared to estimate test length of blocks; and (3) a DFT strategy generation for the shortest test length. We applied REPS to some test designs for a practical LSI that described at RT level. It is found that REPS estimates an accurate test length for an LSI at RTL, i.e. the error of the length is less than 10% from that at the gate level. As a result, the test length generated by the partial scan design method was 37% shorter than that by the conventional full scan design method.
