A simple clock enhanced loop of cascaded electro-absorption modulators （EAMs） and 10 GHz clock recovery modules is presented. The intensity of harmonic of clock-frequency component is analyzed theoretically and veri...A simple clock enhanced loop of cascaded electro-absorption modulators （EAMs） and 10 GHz clock recovery modules is presented. The intensity of harmonic of clock-frequency component is analyzed theoretically and verified experimentally in a 160 Gb/s OTDM 100 km transmission system. The 10 GHz clock component is enhanced obviously before launching into the clock recovery module and the recovered clock signal exhibits low rms jitter of 〈400 fs. Moreover, completely error^-1free （10-12） transmission is observed for more than two hours without using forward error correction technology. The power penalty is about 3.6 dB. The proposed loop has merits of enhancing base clock component, simultaneously de-multiplexing and clock recovery, which make the performance of this loop more stable and high suppression of non-target channels.展开更多
基金Supported by the Fundamental Research Funds for the Central Universities （No 2009YJS005）, the National High-Tech Research and Development Program of China under Grant No 2008AA01Z15, the National Natural Science Foundation of China under Grant No 60877042 and 60837003, Beijing Nova Program （No 2008A026）, and the Natural Science Foundation of Beijing （No 4062027）.
文摘A simple clock enhanced loop of cascaded electro-absorption modulators （EAMs） and 10 GHz clock recovery modules is presented. The intensity of harmonic of clock-frequency component is analyzed theoretically and verified experimentally in a 160 Gb/s OTDM 100 km transmission system. The 10 GHz clock component is enhanced obviously before launching into the clock recovery module and the recovered clock signal exhibits low rms jitter of 〈400 fs. Moreover, completely error^-1free （10-12） transmission is observed for more than two hours without using forward error correction technology. The power penalty is about 3.6 dB. The proposed loop has merits of enhancing base clock component, simultaneously de-multiplexing and clock recovery, which make the performance of this loop more stable and high suppression of non-target channels.
