The defect evolution in InP with the 75 keV H^(+)and 115 keV He^(+)implantation at room temperature after subsequent annealing has been investigated in detail.With the same ion implantation fluence,the He^(+)implantat...The defect evolution in InP with the 75 keV H^(+)and 115 keV He^(+)implantation at room temperature after subsequent annealing has been investigated in detail.With the same ion implantation fluence,the He^(+)implantation caused much broader damage distribution accompanied by much higher out-of-plane strain with respect to the H^(+)implanted InP.After annealing,the H^(+)implanted InP did not show any blistering or exfoliation on the surface even at the high fluence and the H2 molecules were stored in the heterogeneously oriented platelet defects.However,the He molecules were stored into the large bubbles which relaxed toward the free surface,creating blisters at the high fluence.展开更多
Integration of the high-quality Ga Sb layer on an Si substrate is significant to improve the Ga Sb application in optoelectronic integration.In this work,a suitable ion implantation fluence of 5×10^(16)-cm^(-2)H ...Integration of the high-quality Ga Sb layer on an Si substrate is significant to improve the Ga Sb application in optoelectronic integration.In this work,a suitable ion implantation fluence of 5×10^(16)-cm^(-2)H ions for Ga Sb layer transfer is confirmed.Combining the strain change and the defect evolution,the blistering and exfoliation processes of Ga Sb during annealing is revealed in detail.With the direct wafer bonding,the Ga Sb layer is successfully transferred onto a(100)Si substrate covered by 500-nm thickness thermal oxide SiO_(2)layer.After being annealed at 200℃,the Ga Sb layer shows high crystalline quality with only 77 arcsec for the full width at half maximum(FWHM)of the x-ray rocking curve(XRC).展开更多
Strain and stress were simulated using finite element method(FEM)for threeⅢ-V-on-Insulator(Ⅲ-VOI)structures,i.e.,InP/SiO2/Si,InP/Al2O3/SiO2/Si,and GaAs/Al2O3/SiO2/Si,fabricated by ion-slicing as the substrates for o...Strain and stress were simulated using finite element method(FEM)for threeⅢ-V-on-Insulator(Ⅲ-VOI)structures,i.e.,InP/SiO2/Si,InP/Al2O3/SiO2/Si,and GaAs/Al2O3/SiO2/Si,fabricated by ion-slicing as the substrates for optoelectronic devices on Si.The thermal strain/stress imposes no risk for optoelectronic structures grown on InPOI at a normal growth temperature using molecular beam epitaxy.Structures grown on GaAsOI are more dangerous than those on InPOI due to a limited critical thickness.The intermedia Al2O3 layer was intended to increase the adherence while it brings in the largest risk.The simulated results reveal thermal stress on Al2O3 over 1 GPa,which is much higher than its critical stress for interfacial fracture.InPOI without an Al2O3 layer is more suitable as the substrate for optoelectronic integration on Si.展开更多
基金Project supported by the National Key R&D Program of China(Grant No.2017YFE0131300)the National Natural Science Foundation of China(Grant Nos.61874128,61851406,and 11705262)+3 种基金Frontier Science Key Program of Chinese Academy of Sciences(Grant Nos.QYZDY-SSW-JSC032 and ZDBS-LYJSC009)Chinese–Austrian Cooperative R&D Project(Grant No.GJHZ201950),Program of Shanghai Academic Research Leader(Grant No.19XD1404600)K.C.Wong Education Foundation(Grant No.GJTD-2019-11)NCBiR within the Polish–China(Grant No.WPC/130/NIR-Si/2018).
文摘The defect evolution in InP with the 75 keV H^(+)and 115 keV He^(+)implantation at room temperature after subsequent annealing has been investigated in detail.With the same ion implantation fluence,the He^(+)implantation caused much broader damage distribution accompanied by much higher out-of-plane strain with respect to the H^(+)implanted InP.After annealing,the H^(+)implanted InP did not show any blistering or exfoliation on the surface even at the high fluence and the H2 molecules were stored in the heterogeneously oriented platelet defects.However,the He molecules were stored into the large bubbles which relaxed toward the free surface,creating blisters at the high fluence.
基金the National Key Research and Development Program of China(Grant No.2017YFE0131300)the National Natural Science Foundation of China(Grant Nos.U1732268,61874128,11622545,61851406,11705262,61875220,and 61804157)+6 种基金the Frontier Science Key Program of Chinese Academy of Sciences(Grant Nos.QYZDYSSW-JSC032 and ZDBS-LY-JSC009)the Chinese–Austrian Cooperative Research and Development Project(Grant No.GJHZ201950)the Shanghai Science and Technology Innovation Action Plan Program,China(Grant No.17511106202)the Program of Shanghai Academic Research Leader,China(Grant No.19XD1404600)the Shanghai Youth Top Talent Program,Shanghai Sailing Program,China(Grant Nos.19YF1456200 and 19YF1456400)the K.C.Wong Education Foundation,China(Grant No.GJTD2019-11)the NCBiR within the Polish–China(Grant No.WPC/130/NIR-Si/2018)。
文摘Integration of the high-quality Ga Sb layer on an Si substrate is significant to improve the Ga Sb application in optoelectronic integration.In this work,a suitable ion implantation fluence of 5×10^(16)-cm^(-2)H ions for Ga Sb layer transfer is confirmed.Combining the strain change and the defect evolution,the blistering and exfoliation processes of Ga Sb during annealing is revealed in detail.With the direct wafer bonding,the Ga Sb layer is successfully transferred onto a(100)Si substrate covered by 500-nm thickness thermal oxide SiO_(2)layer.After being annealed at 200℃,the Ga Sb layer shows high crystalline quality with only 77 arcsec for the full width at half maximum(FWHM)of the x-ray rocking curve(XRC).
基金Project supported by the National Key Research and Development Program of China(Grant No.2017YFE0131300)the National Natural Science Foundation of China(Grant Nos.U1732268,61874128,11622545,61851406,11705262,and 61804157)+5 种基金the Frontier Science Key Program of the Chinese Academy of Sciences(Grant No.QYZDY-SSW-JSC032)the Chinese-Austrian Cooperative Research and Development Project(Grant No.GJHZ201950)the Science and Technology Innovation Action Plan Program of Shanghai,China(Grant No.17511106202)the Program of Shanghai Academic Research Leader,China(Grant No.19XD1404600)the Sailing Program of Shanghai,China(Grant Nos.19YF1456200 and 19YF1456400)the K C Wong Education Foundation(Grant No.GJTD-2019-11).
文摘Strain and stress were simulated using finite element method(FEM)for threeⅢ-V-on-Insulator(Ⅲ-VOI)structures,i.e.,InP/SiO2/Si,InP/Al2O3/SiO2/Si,and GaAs/Al2O3/SiO2/Si,fabricated by ion-slicing as the substrates for optoelectronic devices on Si.The thermal strain/stress imposes no risk for optoelectronic structures grown on InPOI at a normal growth temperature using molecular beam epitaxy.Structures grown on GaAsOI are more dangerous than those on InPOI due to a limited critical thickness.The intermedia Al2O3 layer was intended to increase the adherence while it brings in the largest risk.The simulated results reveal thermal stress on Al2O3 over 1 GPa,which is much higher than its critical stress for interfacial fracture.InPOI without an Al2O3 layer is more suitable as the substrate for optoelectronic integration on Si.
