摘要
本文介绍了一种基于列级ADC的读出电路设计实现。该读出电路阵列规格为640×512,间距为15μm,列级数字化ADC结构采用三阶增量式Sigma-DeltaADC结构,其量化分辨率为16位,读出电路最大帧频为240Hz,最大功耗250mW,输出方式采用LVDS方式。
A column level ADC based readout circuit design is introduced in this paper.The size of the readout circuit is 640×512,the pitch is 15μm.The column level digital ADC structure adopts a three order incremental Sigma Delta ADC structure,and its quantization resolution is 16 bits.The maximum frame frequency of the readout circuit is 240 Hz,and the maximum power consumption is 250 mW,and the output method is LüDS mode.
作者
李敬国
丁熠
王京飞
LI Jing-guo;DING Yi;WANG Jing-fei(11th Research Institute of CETC,Beijing 100015,China;CETC,Beijing 100000,China)
出处
《激光与红外》
CAS
CSCD
北大核心
2024年第11期1725-1729,共5页
Laser & Infrared
