摘要
研究JPEG2000标准中自适应算术编码器的硬件实现问题,提出一种适合ASIC实现的并行结构,并在FPGA上对其进行了仿真验证.该设计使用VHDL语言在RTL级描述;并以XILINXXC2V8000-5FF1152为基础,在ISE5.2下完成综合及后仿真.在整个JPEG2000设计中,最高工作时钟66MHz,自适应算术编码器处理速度可达到0.25bit/cycle.
FPGA implementation of the adaptive arithmetic encoder in JPEG2000 standard is investigated. A parallel architecture suitable for ASIC implementation is presented, which is simulated and verified on FPGA.The design is described with VHDL at RT level. Based on XILINX XC2V8000-5FF1152, synthesis and postsimulation are conducted with ISE 5.2. The JPEG 2000 encoder system works at 66 MHz, it costs the adaptive arithmetic encoder about 1 cycle to encode 0.25 bit.
出处
《北京理工大学学报》
EI
CAS
CSCD
北大核心
2005年第3期234-238,共5页
Transactions of Beijing Institute of Technology
基金
国家部委预研项目(41308010408)
